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參數(shù)資料
| 型號： | P12C508 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller |
| 中文描述： | 8引腳，8位CMOS微控制器 |
| 文件頁數(shù)： | 21/84頁 |
| 文件大?。?/td> | 526K |
| 代理商： | P12C508 |
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1996 Microchip Technology Inc.
Advance Information
DS40139A-page 21
PIC12C5XX
6.0
TIMER0 MODULE AND
TMR0 REGISTER
The Timer0 module has the following features:
8-bit timer/counter register, TMR0
- Readable and writable
8-bit software programmable prescaler
Internal or external clock select
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of
1:2, 1:4,..., 1:256 are selectable. Section 6.2 details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
0
1
1
0
T0CS
(1)
F
OSC
/4
Programmable
Prescaler
(2)
Sync with
Internal
Clocks
TMR0 reg
PSout
Sync
(2 cycle delay)
PSout
Data bus
8
PSA
(1)
PS2, PS1, PS0
(1)
3
T0SE
GP2/T0CKI
Pin
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