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參數(shù)資料
| 型號： | P12C508 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller |
| 中文描述： | 8引腳，8位CMOS微控制器 |
| 文件頁數(shù)： | 29/84頁 |
| 文件大?。?/td> | 526K |
| 代理商： | P12C508 |
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1996 Microchip Technology Inc.
Advance Information
DS40139A-page 29
PIC12C5XX
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power on reset
0001 1xxx
1111 1111
MCLR reset during normal operation
000u uuuu
1111 1111
MCLR reset during SLEEP
0001 0uuuu
1111 1111
WDT reset during SLEEP
0000 0uuu
1111 1111
WDT reset normal operation
0000 1uuu
1111 1111
Wake-up from SLEEP on pin change
1001 0uuu
1111 1111
Legend:
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘0’.
7.3.1
MCLR ENABLE
This configuration bit when unprogrammed (left in the
programmed, the MCLR function is tied to the internal
V
DD
, and the pin is assigned to be a GPIO. See
Figure 7-7.
FIGURE 7-7:
MCLR SELECT
7.4
Power-On Reset (POR)
The PIC12C5XX family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
A Power-on Reset pulse is generated on-chip when
V
DD
rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, tie the MCLR pin directly
to V
DD
. An internal weak pull-up resistor is imple-
mented using a transistor. Refer to Table 10-5 for the
pull-up resistor ranges. This will eliminate external RC
components usually needed to create a Power-on
Reset. A maximum rise time for V
DD
is specified. See
Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-8.
GP3/MCLR/V
PP
MCLRE
INTERNAL MCLR
WEAK
PULL-UP
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
A power-up example where MCLR is tied to V
SS
is
shown in Figure 7-9. V
DD
is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset T
DRT
msec after MCLR
goes high.
In Figure 7-10, the on-chip Power-On Reset feature is
being used (MCLR and V
DD
are tied together). The
V
DD
is stable before the start-up timer times out and
there is no problem in getting a proper reset. However,
Figure 7-11 depicts a problem situation where V
DD
rises too slowly. The time between when the DRT
senses a high on the GP3/MCLR/V
PP
pin, and when
the GP3/MCLR/V
PP
pin (and V
DD
) actually reach their
full value, is too long. In this situation, when the start-
up timer times out, V
DD
has not reached the V
DD
(min)
value and the chip is, therefore, not guaranteed to
function correctly. For such situations, we recommend
that external RC circuits be used to achieve longer
POR delay times (Figure 7-10).
For additional information refer to Application Notes
“Power-Up Considerations”- AN522 and “Power-up
Trouble Shooting - AN607.
Note:
When the device starts normal operation
(exits the reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
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