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參數(shù)資料
| 型號： | P12C508 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller |
| 中文描述： | 8引腳，8位CMOS微控制器 |
| 文件頁數(shù)： | 34/84頁 |
| 文件大小： | 526K |
| 代理商： | P12C508 |
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PIC12C5XX
DS40139A-page 34
Advanced Information
1996 Microchip Technology Inc.
7.7
Time-Out Sequence, Power Down,
and Wake-up from SLEEP Status Bits
(TO/PD/GPWUF)
The TO, PD, and GPWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) reset, or a MCLR or WDT
reset.
These STATUS bits are only affected by events listed
in Table 7-7.
Table 7-4 lists the reset conditions for the special
function registers, while Table 7-3 lists the reset
conditions for all the registers.
TABLE 7-6:
TO/PD/GPWUF STATUS
AFTER RESET
GPWUF
TO
PD
RESET caused by
WDT wake-up from
SLEEP
WDT time-out (not from
SLEEP)
MCLR wake-up from
SLEEP
Power-up
MCLR not during SLEEP
Wake-up from SLEEP on
pin change
Legend: u = unchanged
Note 1:
The TO, PD, and GPWUF bits main-
tain their status (u) until a reset
occurs. A low-pulse on the MCLR
input does not change the TO, PD,
and GPWUF status bits.
0
0
0
0
0
1
0
1
0
0
0
1
1
u
1
1
u
0
Legend:
TABLE 7-7:
EVENTS AFFECTING TO/PD
STATUS BITS
Event
GPWUF
TO
PD
Remarks
Power-up
WDT Time-out
0
0
1
0
1
u
No effect
on PD
SLEEP instruction
CLRWDT
instruction
Wake-up from
SLEEP on pin
change
Legend: u = unchanged
A WDT time-out will occur regardless of the status of the
TO bit. A SLEEP instruction will be executed, regardless of
the status of the PD bit. Table 7-6 reflects the status of TO
and PD after the corresponding event.
u
u
1
1
0
1
1
1
0
7.8
Reset on Brown-Out
A brown-out is a condition where device power (V
DD
)
dips below its minimum value, but not to zero, and
then recovers. The device should be reset in the event
of a brown-out.
To reset PIC12C5XX devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 7-13 and Figure 7-14.
FIGURE 7-13: BROWN-OUT PROTECTION
CIRCUIT 1
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 2
This circuit will activate reset when V
DD
goes below Vz +
0.7V (where Vz = Zener voltage).
*Refer to Figure 7-7 and Table 10-5 for internal weak pull-
up on MCLR.
33k
10k
40k*
V
DD
MCLR
PIC12C5XX
V
DD
Q1
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when V
DD
is below a certain level such that:
R1
R1 + R2
*Refer to Figure 7-7 and Table 10-5 for internal weak
pull-up on MCLR.
V
DD
= 0.7V
R2
40k
V
DD
MCLR
PIC12C5XX
R1
Q1
V
DD
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