參數(shù)資料
型號(hào)： P12C508
廠商： Microchip Technology Inc.
英文描述： 8-Pin, 8-Bit CMOS Microcontroller
中文描述： 8引腳，8位CMOS微控制器
文件頁數(shù)： 23/84頁
文件大小： 526K
代理商： P12C508
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 23
PIC12C5XX
6.1
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (T
OSC
)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI to be
high for at least 2T
OSC
(and a small RC delay of 20 ns)
and low for at least 2T
OSC
(and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4T
OSC
(and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
6.1.3
OPTION REGISTER EFFECT ON GP2 TRIS
If the option register is set to read TIMER0 from the pin,
the port is forced to an input regardless of the TRIS reg-
ister setting.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Increment Timer0 (Q4)
External Clock Input or
Prescaler Output
(2)
Q1
Q2
Q3 Q4
Q1
Q2
Q3 Q4
Q1
Q2
Q3 Q4
Q1
Q2
Q3 Q4
Small pulse
misses sampling
Timer0
T0
T0 + 1
T0 + 2
External Clock/Prescaler
Output After Sampling
(3)
Note 1:
2:
3:
Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input =
±
4Tosc max.
External clock if no prescaler selected, Prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.
(1)
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