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| 型號(hào)： | P610ARM-KG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 120/173頁(yè) |
| 文件大小： | 897K |
| 代理商： | P610ARM-KG |
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Memory Management Unit
ARM610 Data Sheet
9-16
9.15.1 Alignment fault
If Alignment Fault is enabled (bit 1 in Control Register set), the MMU will generate an
alignment fault on any data word access the address of which is not word-aligned
irrespective of whether the MMU is enabled or not; in other words, if either of virtual
address bits [1:0] are not 0. Alignment fault will not be generated on any instruction
fetch, nor on any byte access. If the access generates an alignment fault, the access
sequence will abort without reference to further permission checks.
9.15.2 Translation fault
There are two types of translation fault: section and page.
1
A Section Translation Fault is generated if the Level One descriptor is marked
as invalid. This happens if bits [1:0] of the descriptor are both 0 or both 1.
2
A Page Translation Fault is generated if the Page Table Entry is marked as
invalid. This happens if bits [1:0] of the entry are both 0 or both 1.
9.15.3 Domain fault
There are two types of domain fault: section and page. In both cases the Level One
descriptor holds the 4-bit Domain field which selects one of the sixteen 2-bit domains
in the Domain Access Control Register. The two bits of the specified domain are then
checked for access permissions as detailed in
·
Table 9-2: Interpreting access
permission (AP) Bitson page 9-7. In the case of a section, the domain is checked once
the Level One descriptor is returned, and in the case of a page, the domain is checked
once the Page Table Entry is returned.
If the specified access is either No Access (00) or Reserved (10) then either a Section
Domain Fault or Page Domain Fault occurs.
9.15.4 Permission fault
There are two types of permission fault: section and sub-page. Permission fault is
checked at the same time as Domain fault. If the 2-bit domain field returns client (01),
then the permission access check is invoked as follows:
section
If the Level One descriptor defines a section-mapped access, then the AP bits
of the descriptor define whether or not the access is allowed according to
·
Table 9-2: Interpreting access permission (AP) Bitson page 9-7. Their
interpretation is dependent upon the setting of the S bit (Control Register bit
8). If the access is not allowed, then a Section Permission fault is generated.
sub-page
If the Level One descriptor defines a page-mapped access, then the Level
Two descriptor specifies four access permission fields (ap3..ap0) each
corresponding to one quarter of the page. Hence for small pages, ap3 is
selected by the top 1Kb of the page, and ap0 is selected by the bottom 1Kb of
the page; for large pages, ap3 is selected by the top 16Kb of the page, and
ap0 is selected by the bottom 16Kb of the page. The selected AP bits are then
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| P610ARM-KW | General purpose 32-bit microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P610ARM-KW | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P6-10R | 制造商:Panduit Corp 功能描述:PANDUIT |
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| P610R-E | 制造商:Panduit Corp 功能描述: |
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