參數(shù)資料
型號: P610ARM-KG
廠商: Zarlink Semiconductor Inc.
英文描述: General purpose 32-bit microprocessor
中文描述: 通用32位微處理器
文件頁數(shù): 131/173頁
文件大?。?/td> 897K
代理商: P610ARM-KG
Bus interface
ARM610 Data Sheet
10-7
Figure 10-7: Translation table-walking sequence (write) for section
10.8.5 Read - Lock - Write
The read-lock-write sequence is generated by a SWP instruction. On the bus it
consists of a read access followed by a write access to the same address, and both
are treated as nonsequential accesses. The cycle is differentiated by the
LOCK
has the timing of address, ie. it goes HIGH in the HIGH phase of
start of the read access. However, it always goes LOW at the end of the write access,
even if the following cycle is an idle cycle (unless of course the following access was
a read-lock-write sequence).
LOCK
MCLK
signal.
at the
Figure 10-8: Read - locked - write
MCLK
A[31:0]
nMREQ
nRW
WRITE
D[31:0]
READ
D[31:0]
Level 1 Address
Physical Address
Section Descriptor
Write Data
MCLK
A[31:0]
nMREQ
D[31:0]
address
LOCK
nRW
write
read
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P610ARM-KW 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor
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