參數(shù)資料
型號： P610ARM-KG
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 142/173頁
文件大?。?/td> 897K
代理商： P610ARM-KG
Boundary-Scan Test Interface
ARM610 Data Sheet
11-8
11.7.1 Bypass register
Purpose: This is a single bit register which can be selected as the path between
and
TDO
to allow the device to be bypassed during boundary-scan testing.
TDI
Length: 1 bit
Operating Mode: When the BYPASS instruction is the current instruction in the
instruction register, serial data is transferred from
TDI
to
TDO
in the SHIFT-DR state
with a delay of one
TCK
cycle.
There is no parallel output from the bypass register.
A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR
state.
11.7.2 ARM610 Device Identification (ID) Code register
Purpose: This register is used to read the 32-bit device identification code. No
programmable supplementary identification code is provided.
Length: 32 bits
The format of the ID register is as follows:
The Device Identification Code for the Zarlink P610ARM-B/KG/FPNR is 1 EA1D 06F.
Operating Mode: When the IDCODE instruction is current, the ID register is selected
as the serial path between
TDI
and
TDO
.
There is no parallel output from the ID register.
The 32-bit device identification code is loaded into the ID register from its parallel
inputs during the CAPTURE-DR state.
11.7.3 ARM610 Boundary-Scan (BS) register
Purpose: The BS register consists of a serially connected set of cells around the
periphery of the device, at the interface between the core logic and the system input/
output pads. This register can be used to isolate the core logic from the pins and then
apply tests to the core logic, or conversely to isolate the pins from the core logic and
then drive or monitor the system pins.
Operating modes: The BS register is selected as the register to be connected between
TDI
and
TDO
only during the SAMPLE/PRELOAD, EXTEST and INTEST instructions.
Values in the BS register are used, but are not changed, during the CLAMP and
CLAMPZ instructions.
In the normal (system) mode of operation, straight-through connections between the
core logic and pins are maintained and normal system operation is unaffected.
0
1
11
12
27
28
31
1
Manufacturer Identity
Part Number
Version
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