參數(shù)資料
型號： P610ARM-KG
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 24/173頁
文件大?。?/td> 897K
代理商： P610ARM-KG
Programmer’s Model
ARM610 Data Sheet
3-8
When either a prefetch or data abort occurs, ARM610 performs the following:
1
Saves the address of the
(for data aborts) in R14_abt; saves CPSR in SPSR_abt.
aborted instruction plus 4 (for prefetch
aborts) or 8
2
Forces M[4:0]=10111 (Abort mode) and sets the I bit in the CPSR.
3
Forces the PC to fetch the next instruction from either address 0x0C (prefetch
abort) or address 0x10 (data
abort).
To return after fixing the reason for the
abort, use SUBS PC,R14_abt,#4 (for a prefetch
abort) or SUBS PC,R14_abt,#8 (for a data abort). This will restore both the PC and the
CPSR and retry the
aborted instruction.
The
implemented when suitable memory management software is available. The
processor is allowed to generate arbitrary addresses, and when the data at an address
is unavailable the MMU signals an
abort. The processor traps into system software
which must work out the cause of the
abort, make the requested data available, and
retry the
aborted instruction. The application program needs no knowledge of the
amount of memory available to it, nor is its state in any way affected by the abort.
abort mechanism allows a
demand paged virtual memory system
to be
Note that there are restrictions on the use of the external abort pin. See
Memory Management Unit
.
·
Chapter 9,
3.5.4 Software interrupt
The software interrupt instruction (SWI) is used for getting into Supervisor mode,
usually to request a particular supervisor function. When a SWI is executed, ARM610
performs the following:
1
Saves the address of the SWI instruction plus 4 in R14_svc; saves CPSR in
SPSR_svc
2
Forces M[4:0]=10011 (Supervisor mode) and sets the I bit in the CPSR
3
Forces the PC to fetch the next instruction from address 0x08
To return from a SWI, use MOVS PC,R14_svc. This will restore the PC and CPSR and
return to the instruction following the SWI.
3.5.5 Undefined instruction trap
When the ARM610 comes across an instruction which it cannot handle (see
4, Instruction Set
), it offers it to any coprocessors which may be present. If a
coprocessor can perform this instruction but is busy at that time, ARM610 will wait until
the coprocessor is ready or until an interrupt occurs. If no coprocessor can handle the
instruction then ARM610 will take the undefined instruction trap.
·
Chapter
The trap may be used for software emulation of a coprocessor in a system which does
not have the coprocessor hardware, or for general purpose instruction set extension
by software emulation.
相關PDF資料
PDF描述
P610ARM-KW General purpose 32-bit microprocessor
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相關代理商/技術參數(shù)
參數(shù)描述
P610ARM-KW 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor
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