參數(shù)資料
型號: P610ARM-KG
廠商: Zarlink Semiconductor Inc.
英文描述: General purpose 32-bit microprocessor
中文描述: 通用32位微處理器
文件頁數(shù): 98/173頁
文件大?。?/td> 897K
代理商: P610ARM-KG
Instruction and Data Cache (IDC)
ARM610 Data Sheet
6-4
6.7
IDC Enable/Disable and Reset
The IDC is automatically disabled and flushed on
read accesses will cause lines to be placed in the cache. If subsequently disabled, no
new lines will be placed in the cache, and the cache is not searched, but, updateable
write operations will continue to operate, thus maintaining consistency with the
external memory. If the cache is subsequently re-enabled, it must be flushed if data
already in the cache no longer matches that in external memory.
nRESET
. Once enabled, cacheable
6.7.1 To enable the IDC
To enable the IDC, make sure that the MMU is enabled first by setting bit 0 in Control
Register, then enable the IDC by setting bit 2 in Control Register. The MMU and IDC
may be enabled simultaneously with a single control register write.
6.7.2 To disable the IDC
To disable the IDC clear bit 2 in Control Register.
Note
Updateable writes continue but no linefetches are performed. To fully inhibit the
cache's operation it should be disabled and then flushed to ensure it contains no valid
entries.
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