參數(shù)資料
型號: P610ARM-KG
廠商: Zarlink Semiconductor Inc.
英文描述: General purpose 32-bit microprocessor
中文描述: 通用32位微處理器
文件頁數(shù): 62/173頁
文件大?。?/td> 897K
代理商: P610ARM-KG
Instruction Set - LDR, STR
ARM610 Data Sheet
4-34
O
4.8.8 Assembler syntax
<LDR|STR>{cond}<H|SH|SB> Rd,<address>
LDR
load from memory into a register
STR
Store from a register into memory
{cond}
two-character condition mnemonic. See
·
Table 4-2: Condition code
summaryon page 4-6.
H
Transfer halfword quantity
SB
Load sign extended byte (Only valid for LDR)
SH
Load sign extended halfword (Only valid for LDR)
Rd
is an expression evaluating to a valid register number.
<address> can be:
1
An expression which generates an address:
<expression>
The assembler will attempt to generate an instruction using
the PC as a base and a corrected immediate offset to
address the location given by evaluating the expression. This
will be a PC relative, pre-indexed address. If the address is
out of range, an error will be generated.
2
A pre-indexed addressing specification:
[Rn]
offset of zero
[Rn,<#expression>]{!}
offset of <expression> bytes
[Rn,{+/-}Rm]{!}
offset of +/- contents of
index register
3
A post-indexed addressing specification:
[Rn],<#expression>
offset of <expression> bytes
[Rn],{+/-}Rm
offset of +/- contents of
index register.
Rn and Rm are expressions evaluating to a register number.
If Rn is R15 then the assembler will subtract 8 from the offset
value to allow for ARM610 pipelining. In this case base write-
back should not be specified.
{!}
writes back the base register (set the W bit) if ! is present.
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