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參數(shù)資料
| 型號： | PCI1221GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | KPT 11C 11#16 SKT PLUG |
| 中文描述： | PC卡控制器 |
| 文件頁數(shù)： | 110/123頁 |
| 文件大小： | 1659K |
| 代理商： | PCI1221GHK |
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110
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
socket power management register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Socket power management
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Socket power management
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Description: This register provides power management control over the socket through a mechanism for
slowing or stopping the clock on the card interface when the card is idle. See Table 58 for a
complete description of the register contents.
Socket power management
Read only, read/write (see individual bit descriptions)
CardBus socket address + 20h
0000 0000h
Table 58. Socket Power Management Register
BIT
SIGNAL
TYPE
FUNCTION
31-26
RSVD
R
Reserved. Bits 31-26 are read only and return 0s when read.
25
SKTACCES
R
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
0 = A PC card access has not occurred (default).
1 = A PC card access has occurred.
24
SKTMODE
R
Socket mode status. This bit provides clock mode information.
0 = Clock is operating normally.
1 = Clock frequency has changed.
23-17
RSVD
R
Reserved. Bits 23-17 are read only and return 0s when read.
16
CLKCTRLEN
R/W
CardBus clock control enable. When bit 16 is set, clock control (CLKCTRL bit 0) is enabled.
0 = Clock control is disabled (default).
1 = Clock control is enabled.
15-1
RSVD
R
Reserved. Bits 15-1 are read only and return 0s when read.
0
CLKCTRL
R/W
CardBus clock control. This bit determines whether the CB CLKRUN protocol will attempt to stop or slow
the CB clock during idle states. Bit 16 enables this bit.
0 = Allows CB CLKRUN protocol to stop the CB clock (default).
1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16.
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