![](http://datasheet.mmic.net.cn/330000/PCI1221GHK_datasheet_16443867/PCI1221GHK_45.png)
PCI1221 GHK/PDV
PC CARD CONTROLLERS
SCPS042 – JULY 1998
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
vendor ID register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Vendor ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
Register:
Type:
Offset:
Default:
Description: This 16-bit read-only register contains a value allocated by the PCI SIG (special interest
group) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is
104Ch.
Vendor ID
Read only
00h (functions 0, 1)
104Ch
device ID register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Device ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
1
0
1
0
1
1
0
0
0
0
0
1
1
0
0
1
Register:
Type:
Offset:
Default:
Description: This 16-bit read-only register contains a value assigned to the PCI1221 by TI. The device
identification for the PCI1221 is AC19h.
Device ID
Read only
02h (functions 0, 1)
AC19h
command register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Command
Type
R
R
R
R
R
R
R
R/W
R
R/W
R
R
R
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Description: The command register provides control over the PCI1221 interface to the PCI bus. All bit
functions adhere to the definitions in PCI Local Bus Specification 2.2. None of the bit functions
in this register are shared between the two PCI1221 PCI functions. Two command registers
exist in the PCI1221, one for each function. Software must manipulate the two PCI1221
functions as separate entities when enabling functionality through the command register. The
SERR_EN and PERR_EN enable bits in this register are internally wired-OR between the two
functions, and these control bits appear separately according to their software function. See
Table 16 for the complete description of the register contents.
Command
Read only, read/write (see individual bit descriptions)
04h
0000h