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參數(shù)資料
| 型號(hào)： | PCI1221GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | KPT 11C 11#16 SKT PLUG |
| 中文描述： | PC卡控制器 |
| 文件頁(yè)數(shù)： | 46/123頁(yè) |
| 文件大小： | 1659K |
| 代理商： | PCI1221GHK |
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PCI1221 GHK/PDV
PC CARD CONTROLLERS
SCPS042 – JULY 1998
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 16. Command Register
BIT
SIGNAL
TYPE
FUNCTION
15–10
RSVD
R
Reserved. Bits 15–10 are read only and return 0s when read. Write transactions have no effect.
9
FBB_EN
R
Fast back-to-back enable. The PCI1221 does not generate fast back-to-back transactions; therefore, bit
9 is read only and returns 0s when read.
8
SERR_EN
R/W
System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set
for the PCI1221 to report address parity errors.
0 = Disable SERR output driver (default)
1 = Enable SERR output driver
7
STEP_EN
R
Address/data stepping control. The PCI1221 does not support address/data stepping, and bit 7 is
hardwired to 0. Write transactions to this bit have no effect.
6
PERR_EN
R/W
Parity error response enable. Bit 6 controls the PCI1221’s response to parity errors through PERR. Data
parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting
SERR.
0 = PCI1221 ignores detected parity error (default)
1 = PCI1221 responds to detected parity errors
5
VGA_EN
R
VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette
registers. The PCI1221 does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit
5 is read only and returns 0 when read. Write transactions to this bit have no effect.
4
MWI_EN
R
Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory
write and Invalidate commands. The PCI1221 controller does not support memory write and invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 is read only
and returns 0 when read. Write transactions to this bit have no effect.
3
SPECIAL
R
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1221 does
not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 is read only and returns
0 when read. Write transactions to this bit have no effect.
2
MAST_EN
R/W
Bus master control. Bit 2 controls whether or not the PCI1221 can act as a PCI bus initiator (master). The
PCI1221 can take control of the PCI bus only when this bit is set.
0 = Disables the PCI1221’s ability to generate PCI bus accesses (default)
1 = Enables the PCI1221’s ability to generate PCI bus accesses
1
MEM_EN
R/W
Memory space enable. Bit 1 controls whether or not the PCI1221 can claim cycles in PCI memory space.
0 = Disables the PCI1221’s response to memory space accesses (default)
1 = Enables the PCI1221’s response to memory space accesses
0
IO_EN
R/W
I/O space control. Bit 0 controls whether or not the PCI1221 can claim cycles in PCI I/O space.
0 = Disables the PCI1221 from responding to I/O space accesses (default)
1 = Enables the PCI1221 to respond to I/O space accesses
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1221PDV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PCI1225 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PC CARD CONTROLLERS |
| PCI1225GHK | 制造商:Texas Instruments 功能描述: |
| PCI1225PDV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| PCI-1240U | 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:4-axis Stepping and Servo Motor Control Universal PCI Card |
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