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參數(shù)資料
| 型號(hào)： | PCI1221GHK |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 英文描述： | KPT 11C 11#16 SKT PLUG |
| 中文描述： | PC卡控制器 |
| 文件頁(yè)數(shù)： | 115/123頁(yè) |
| 文件大?。?/td> | 1659K |
| 代理商： | PCI1221GHK |
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115
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CLOAD includes the typical load-circuit distributed capacitance
VLOAD– VOL
CLOAD
Test
Point
Timing
Input
(see Note A)
Out-of-Phase
Output
tpd
50% VCC
50% VCC
VCC
0 V
0 V
0 V
0 V
0 V
VOL
th
tsu
VOH
VOH
VOL
High-Level
Input
Low-Level
Input
tw
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
tpd
tpd
tpd
VLOAD
IOH
IOL
From Output
Under Test
90% VCC
10% VCC
tr
tf
Output
Control
(low-level
enabling)
Waveform 1
(see Notes
B and C)
Waveform 2
(see Notes
B and C)
VOL
VOH
VOH– 0.3 V
tPZL
tPZH
tPLZ
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOL+ 0.3 V
0 V
0 V
50% VCC
50% VCC
ten
tdis
tpd
tPZH
tPZL
tPHZ
tPLZ
CLOAD
(pF)
IOL
(mA)
TIMING
PARAMETER
50
8
–8
0
3
1.5
50
8
8
–8
–8
LOAD CIRCUIT PARAMETERS
= 50
, where VOL = 0.6 V, IOL = 8 mA
IOL
50
IOH
(mA)
VLOAD
(V)
Data
Input
In-Phase
Output
Input
(see Note A)
VCC
VCC
VCC
50% VCC
50% VCC
50% VCC
50% VCC
VCC
VCC
50% VCC
50% VCC
50% VCC
50% VCC
VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, ZO = 50
, tr = 6 ns.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For tPLZ and tPHZ, VOL and VOH are measured values.
50% VCC
Figure 24. Load Circuit and Voltage Waveforms
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