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參數(shù)資料
| 型號(hào)： | PCI1221GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | KPT 11C 11#16 SKT PLUG |
| 中文描述： | PC卡控制器 |
| 文件頁(yè)數(shù)： | 89/123頁(yè) |
| 文件大?。?/td> | 1659K |
| 代理商： | PCI1221GHK |
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89
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ExCA card status-change-interrupt configuration register (index 05h)
Bit
7
6
5
4
3
2
1
0
Name
ExCA status-change-interrupt configuration
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
ExCA card status-change-interrupt configuration
Read/write (see individual bit descriptions)
CardBus socket address + 805h; Card A ExCA offset 05h
Card B ExCA offset 45h
Default:
Description: This register controls interrupt routing for card status-change interrupts, as well as masking
CSC interrupt sources. See Table 44 for a complete description of the register contents.
00h
Table 44. ExCA Card Status-Change-Interrupt Configuration Register (Index 05h)
BIT
SIGNAL
TYPE
FUNCTION
7-4
CSCSELECT
R/W
Interrupt select for card status change. Bits 7-4 select the interrupt routing for card status change
interrupts. This field is encoded as:
0000 = No interrupt routing (default)
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
3
CDEN
R/W
Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enables interrupts on CD1 or CD2 line changes
2
READYEN
R/W
Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host
interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
1
BATWARNEN
R/W
Battery Warning Enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
0
BATDEADEN
R/W
Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI1410GHK | PC CARD CONTROLLERS |
| PCI1510GVF | PC CARD CONTROLLERS |
| PCI1510ZVF | PC CARD CONTROLLERS |
| PCI1520I | PC CARD CONTROLLERS |
| PCI4410A | PC CARD AND OHCI CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1221PDV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PCI1225 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PC CARD CONTROLLERS |
| PCI1225GHK | 制造商:Texas Instruments 功能描述: |
| PCI1225PDV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| PCI-1240U | 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:4-axis Stepping and Servo Motor Control Universal PCI Card |
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