![](http://datasheet.mmic.net.cn/330000/PCI1221GHK_datasheet_16443867/PCI1221GHK_44.png)
PCI1221 GHK/PDV
PC CARD CONTROLLERS
SCPS042 – JULY 1998
44
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PC Card controller programming model
This section describes the PCI1221 PCI configuration registers that make up the 256-byte PCI configuration
header for each PCI1221 function. As noted, some bits are global in nature and should be accessed only
through function 0.
PCI configuration registers (functions 0 and 1)
The PCI1221 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1.
The configuration header is compliant with the PCI specification as a CardBus bridge header and is PC 99
compliant as well. Table 15 shows the PCI configuration header, which includes both the predefined portion of
the configuration space and the user-definable registers.
Table 15. PCI Configuration Registers (Functions 0 and 1)
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class code
Revision ID
08h
BIST
Header type
Latency timer
Cache line size
0Ch
CardBus socket/ExCA base address
10h
Secondary status
Reserved
Capability pointer
14h
CardBus latency timer
Subordinate bus number
CardBus bus number
PCI bus number
18h
CardBus Memory base register 0
1Ch
CardBus Memory limit register 0
20h
CardBus Memory base register 1
24h
CardBus Memory limit register 1
28h
CardBus I/O base register 0
2Ch
CardBus I/O limit register 0
30h
CardBus I/O base register 1
34h
CardBus I/O limit register 1
38h
Bridge control
Interrupt pin
Interrupt line
3Ch
Subsystem ID
Subsystem vendor ID
40h
PC Card 16-bit I/F legacy-mode base address
44h
Reserved
48h–7Ch
System control
80h
Reserved
84h–88h
Multifunction routing
8Ch
Diagnostic
Device control
Card control
Retry status
90h
Reserved
94h-9Fh
Power-management capabilities
Next-item pointer
Capability ID
A0h
PM data
PMCSR bridge support
extensions
Power-management control/status
A4h
General-purpose event enable
General-purpose event status
A8h
General-purpose output
General-purpose input
ACh
Serial bus control/status
Serial bus slave address
Serial bus index
Serial bus data
B0h
Reserved
B4h–FCh