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參數(shù)資料
| 型號(hào)： | PCI4510PDV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER |
| 中文描述： | PC卡和綜合1394A端口- 2000 OHCI的兩個(gè)端口物理層/鏈路層控制器 |
| 文件頁數(shù)： | 15/220頁 |
| 文件大?。?/td> | 1356K |
| 代理商： | PCI4510PDV |
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11
1 Introduction
The Texas Instruments PCI4510 device is an integrated single-socket PC Card controller with an IEEE 1394 open
host controller link-layer controller (LLC) and two-port 1394 PHY. This high performance integrated solution provides
the latest in both PC Card and IEEE 1394 technology.
1.1
Description
The Texas Instruments PCI4510 device is compliant with
PCI Local Bus Specification
. Function 0 provides the
independent PC Card socket controller compliant with the latest
PC Card Standard
s. The PCI4510 device provides
features that make it the best choice for bridging between the PCI bus and PC Cards, and supports either 16-bit or
CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required.
There are no PCMCIA card and socket service software changes required to move systems from the existing
CardBus socket controller to the PCI4510 device. The PCI4510 device is register compatible with the Intel
82365SL–DF ExCA controller and implements the host interface defined in the
PC Card Standard
. The PCI4510
internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum
performance. Independent buffering and the pipeline architecture provides an unsurpassed performance level with
sustained bursting. The PCI4510 device can be programmed to accept posted writes to improve bus utilization. All
card signals are internally buffered to allow hot insertion and removal without external buffering.
Function 1 of the PCI4510 device is an integrated IEEE 1394a-2000 open host controller interface (OHCI)
PHY/link-layer controller (LLC) device that is fully compliant with the
PCI Local Bus Specification
, the
PCI Bus Power
Management Interface Specification
, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the
1394 Open Host
Controller Interface Specification
. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus
at 100M bits/s, 200M bits/s, and 400M bits/s. The PCI4510 device provides two 1394 ports that have separate cable
bias (TPBIAS). The PCI4510 device also supports the IEEE Std 1394a-2000 power-down features for
battery-operated applications and arbitration enhancements.
As required by the
1394 Open Host Controller Interface Specification
and IEEE Std 1394a-2000, internal control
registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration
cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the PCI4510 device is
compliant with the
PCI Bus Power Management Interface Specification
as specified by the
PC 2001 Design Guide
requirements. The PCI4510 device supports the D0, D1, D2, and D3 power states.
The PCI4510 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at
132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided
to buffer the IEEE 1394 data.
The PCI4510 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2
performance. The PCI4510 device also provides multiple isochronous contexts, multiple cacheline burst transfers,
advanced internal arbitration, and bus-holding buffers.
The PCI4510 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node
in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for initialization and
arbitration, and for packet reception and transmission.
The PCI4510 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external
clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock
signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal
is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data. Data bits
to be transmitted through the cable ports are received from the integrated LLC and are latched internally in
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI4510RGVF | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Card & Integrated 1394a-2000 OHCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4510RZVF | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Card & Integrated 1394a-2000 OHCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4510ZHK | 制造商:Texas Instruments 功能描述: |
| PCI4512ZHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Integ sngl-socket PC Card controller RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4515 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
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