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| 型號： | PCI4510PDV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER |
| 中文描述： | PC卡和綜合1394A端口- 2000 OHCI的兩個端口物理層/鏈路層控制器 |
| 文件頁數(shù)： | 190/220頁 |
| 文件大?。?/td> | 1356K |
| 代理商： | PCI4510PDV |
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840
8.42 Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the isochronous
transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,
…
, 7). See Table 833 for a complete description of the register contents.
Bit
Name
Type
Default
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Isochronous transmit context control
RSC
RSC
RSC
X
X
X
RSCU
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Bit
Name
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Isochronous transmit context control
R
R
0
0
RSC
0
R
0
R
0
RSU
X
RU
0
RU
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Offset:
Isochronous transmit context control
200h + (16 * n)
set register
204h + (16 * n)
clear register
Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only
XXXX X0XXh
Table 833. Isochronous Transmit Context Control Register Description
Type:
Default:
BIT
31
FIELD NAME
cycleMatchEnable
TYPE
RSCU
DESCRIPTION
When bit 31 is set to 1, processing occurs such that the packet described by the context first
descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field
(bits 3016). The cycleMatch field (bits 3016) must match the low-order two bits of cycleSeconds
and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before
isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead,
the processing of the first descriptor block may begin slightly in advance of the actual cycle in which
the first packet is transmitted.
The effects of this bit, however, are impacted by the values of other bits in this register and are
explained in the
1394 Open Host Controller Interface Specification.
Once the context has become
active, hardware clears this bit.
3016
cycleMatch
RSC
This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle
timer register at OHCI offset F0h (see Section 8.34) cycleSeconds field (bits 3125) and the
cycleCount field (bits 2412). If bit 31 (cycleMatchEnable) is set to 1, then this isochronous transmit
DMA context becomes enabled for transmits when the low-order two bits of the isochronous cycle
timer register at OHCI offset F0h cycleSeconds field (bits 3125) and the cycleCount field
(bits 2412) value equal this field (cycleMatch) value.
15
run
RSC
Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The PCI4510 device changes this bit only on a system (hardware) or
software reset.
1413
12
RSVD
wake
R
Reserved. Bits 14 and 13 return 0s when read.
Software sets bit 12 to 1 to cause the PCI4510 device to continue or resume descriptor processing.
The PCI4510 device clears this bit on every descriptor fetch.
RSU
11
dead
RU
The PCI4510 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software
clears bit 15 (run) to 0.
10
98
75
40
active
RSVD
spd
event code
RU
R
RU
RU
The PCI4510 device sets bit 10 to 1 when it is processing descriptors.
Reserved. Bits 9 and 8 return 0s when read.
This field in not meaningful for isochronous transmit contexts.
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are:
ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true:
1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1.
2. Bits 40 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout.
3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1.
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