![](http://datasheet.mmic.net.cn/330000/PCI4510PDV_datasheet_16443873/PCI4510PDV_33.png)
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The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 26. Power Supply Terminals
TERMINAL
NAME
NUMBER
GHK
I/O
DESCRIPTION
PDV
RGVF
GND
6, 24, 39, 62,
114, 128, 143,
162, 180, 195
E01, K01, N01,
W06, P19, K19,
G19, A15, A10,
A07
G07, G08, G13,
H13, J09, J10,
J11, K09, K10,
K11, L08, L09,
L10, L11, L12,
M08
Device ground terminals
VCC
14, 34, 47, 70,
123, 138, 151,
170, 190, 203
G01, M01, R01,
W08, L19, H19,
E19, A13, A08,
A05
H08, H09, H10,
H11, H12, J08,
J12, K08, K12,
M07, M09, M10,
M12, N07
Power supply terminal for I/O and internal voltage regulator
VCCCB
146, 175
G14, A11
A05, A11
Clamp voltage for PC CardBus interface. Matches card signal-
ing environment, 5 V or 3.3 V
VCCP
VR_EN
29, 58
L01, W05
W03, W10
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
15
H05
H02
I
Internal voltage regulator enable. Active low
VR_PORT
13, 124
G02, L18
H01, M19
I/O
Internal voltage regulator input/output. When VR_EN is low,
the regulator is enabled and these terminals are outputs. The
two VR_PORT terminals must be tied together and connected
to ground through a 0.1
μ
F bypass capacitor. When VR_EN is
high, the regulator is disabled and these terminals are inputs
for an external 1.8-V core power source.
Table 27. PC Card Power Switch Terminals
TERMINAL
NAME
NUMBER
GHK
I/O
DESCRIPTION
PDV
RGVF
VD1/VCCD0
VD0/VCCD1
206
205
E06
B05
L06
L05
O
Logic controls to the TPS2211A or TPS2221 PC Card power interface switch to control
AVCC
VD3/VPPD0
VD2/VPPD1
208
207
A04
C05
N02
N01
O
Logic controls to the TPS2211A or TPS2221 PC Card power interface switch to control AVPP
Table 28. PCI System Terminals
TERMINAL
NAME
NUMBER
GHK
I/O
DESCRIPTION
PDV
RGVF
GRST
17
H02
T01
I
Global reset. When the global reset is asserted, the GRST signal causes the PCI4510 device to
place all output buffers in a high-impedance state and reset all internal registers. When GRST is
asserted, the device is completely in its default state. GRST must be connected to POWER_OK.
PCLK
18
H01
P05
I
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled
at the rising edge of PCLK.
PRST
16
H03
R03
I
PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI4510 device to place all
output buffers in a high-impedance state and reset internal registers. When PRST is asserted, the
device is completely nonfunctional. After PRST is deasserted, the PCI4510 device is in a default
state.
When SUSPEND and PRST are asserted, the device is protected from PRST clearing the internal
registers. All outputs are placed in a high-impedance state, but the contents of the registers are
preserved.