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參數(shù)資料
| 型號： | PCI4510PDV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER |
| 中文描述： | PC卡和綜合1394A端口- 2000 OHCI的兩個(gè)端口物理層/鏈路層控制器 |
| 文件頁數(shù)： | 75/220頁 |
| 文件大?。?/td> | 1356K |
| 代理商： | PCI4510PDV |
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43
4.4
Command Register
The PCI command register provides control over the PCI4510 interface to the PCI bus. All bit functions adhere to the
definitions in the
PCI Local Bus Specification
(see Table 43). None of the bit functions in this register are shared
among the PCI4510 PCI functions. Three command registers exist in the PCI4510 device, one for each function.
Software manipulates the PCI4510 functions as separate entities when enabling functionality through the command
register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the three
functions, and these control bits appear to software to be separate for each function.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Command
Type
R
R
R
R
R
R
R
RW
R
RW
RW
R
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read-only, Read/Write
0000h
Table 43. Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
1510
RSVD
R
Reserved. Bits 1510 return 0s when read.
9
FBB_EN
R
Fast back-to-back enable. The PCI4510 device does not generate fast back-to-back transactions; therefore,
this bit is read-only. This bit returns a 0 when read.
8
SERR_EN
RW
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
to 1 for the PCI4510 device to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
7
STEP_EN
R
Address/data stepping control. The PCI4510 device does not support address/data stepping, and this bit
is hardwired to 0. Writes to this bit have no effect.
6
PERR_EN
RW
Parity error response enable. This bit controls the PCI4510 device response to parity errors through the
PERR signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated
by asserting SERR.
0 = PCI4510 device ignores detected parity errors (default).
1 = PCI4510 device responds to detected parity errors.
5
VGA_EN
RW
VGA palette snoop. When set to 1, palette snooping is enabled (that is, the PCI4510 device does not
respond to palette register writes and snoops the data). When the bit is 0, the PCI4510 device treats all
palette accesses like all other accesses.
4
MWI_EN
R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI4510 controller does not support memory write-and-invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
3
SPECIAL
R
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI4510 device
does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when
read. Writes to this bit have no effect.
2
MAST_EN
RW
Bus master control. This bit controls whether or not the PCI4510 device can act as a PCI bus initiator
(master). The PCI4510 device can take control of the PCI bus only when this bit is set.
0 = Disables the PCI4510 ability to generate PCI bus accesses (default)
1 = Enables the PCI4510 ability to generate PCI bus accesses
1
MEM_EN
RW
Memory space enable. This bit controls whether or not the PCI4510 device can claim cycles in PCI memory
space.
0 = Disables the PCI4510 response to memory space accesses (default)
1 = Enables the PCI4510 response to memory space accesses
0
IO_EN
RW
I/O space control. This bit controls whether or not the PCI4510 device can claim cycles in PCI I/O space.
0 = Disables the PCI4510 device from responding to I/O space accesses (default)
1 = Enables the PCI4510 device to respond to I/O space accesses
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI4510RGVF | 功能描述:外圍驅(qū)動器與原件 - PCI Card & Integrated 1394a-2000 OHCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4510RZVF | 功能描述:外圍驅(qū)動器與原件 - PCI Card & Integrated 1394a-2000 OHCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4510ZHK | 制造商:Texas Instruments 功能描述: |
| PCI4512ZHK | 功能描述:外圍驅(qū)動器與原件 - PCI Integ sngl-socket PC Card controller RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4515 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
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