參數(shù)資料
型號(hào)： PCI4510PDV
廠商： Texas Instruments, Inc.
英文描述： PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER
中文描述： PC卡和綜合1394A端口- 2000 OHCI的兩個(gè)端口物理層/鏈路層控制器
文件頁(yè)數(shù)： 191/220頁(yè)
文件大?。?/td> 1356K
代理商： PCI4510PDV
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841
8.43 Isochronous Transmit Context Command Pointer Register
The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor
block that the PCI4510 device accesses when software enables an isochronous transmit context by setting bit 15
(run) in the isochronous transmit context control register (see Section 8.42) to 1. The isochronous transmit DMA
context command pointer can be read when a context is active. The n value in the following register addresses
indicates the context number (n = 0, 1, 2, 3,
…
, 7).
Bit
Name
Type
Default
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Isochronous transmit context command pointer
R
R
R
X
X
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Bit
Name
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Isochronous transmit context command pointer
R
R
R
X
X
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Offset:
Type:
Default:
Isochronous transmit context command pointer
20Ch + (16 * n)
Read-only
XXXX XXXXh
8.44 Isochronous Receive Context Control Register
The isochronous receive context control set/clear register controls options, state, and status for the isochronous
receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
See Table 834 for a complete description of the register contents.
Bit
Name
Type
Default
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Isochronous receive context control
R
R
R
0
0
0
RSC
X
RSC
X
RSCU
X
RSC
X
RSC
X
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
Name
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Isochronous receive context control
RU
R
R
0
0
0
RSCU
0
R
0
R
0
RSU
X
RU
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Offset:
Isochronous receive context control
400h + (32 * n)
404h + (32 * n)
Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only
XX00 X0XXh
Table 834. Isochronous Receive Context Control Register Description
set register
clear register
Type:
Default:
BIT
31
FIELD NAME
bufferFill
TYPE
RSC
DESCRIPTION
When bit 31 is set to 1, received packets are placed back-to-back to completely fill each receive
buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28
(multiChanMode) is set to 1, then this bit must also be set to 1. The value of this bit must not be
changed while bit 10 (active) or bit 15 (run) is set to 1.
When bit 30 is set to 1, received isochronous packets include the complete 4-byte isochronous
packet header seen by the link layer. The end of the packet is marked with a xferStatus in the first
doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart
packet.
When this bit is cleared, the packet header is stripped from received isochronous packets. The
packet header, if received, immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set to 1.
30
isochHeader
RSC
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