![](http://datasheet.mmic.net.cn/330000/PCI6420_datasheet_16443877/PCI6420_33.png)
2
–
17
Table 2
–
11. 16-Bit PC Card Interface Control Terminals (Continued)
SOCKET A TERMINAL
SOCKET B TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
NAME
NUMBER
A_REG
B04
B_REG
D18
O
Attribute memory select. REG remains high for all common memory accesses.
When REG is asserted, access is limited to attribute memory (OE or WE active)
and to the I/O space (IORD or IOWR active). Attribute memory is a separately
accessed section of card memory and is generally used to record card capacity
and other configuration and attribute information.
A_RESET
C06
B_RESET
E19
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
A_VS1
A_VS2
C04
E07
B_VS1
B_VS2
C18
F18
I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction
with each other, determine the operating voltage of the PC Card.
A_WAIT
B02
B_WAIT
B18
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion
of the memory or I/O cycle in progress.
A_WE
E09
B_WE
H19
O
Write enable. WE is used to strobe memory write data into 16-bit memory PC
Cards. WE is also used for memory PC Cards that employ programmable
memory technologies.
A_WP
(IOIS16)
C02
B_WP
(IOIS16)
B17
I
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status
of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP
is used for the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the
16-bit PC Card when the address on the bus corresponds to an address to
which the 16-bit PC Card responds, and the I/O port that is addressed is
capable of 16-bit accesses.
Table 2
–
12. CardBus PC Card Interface System Terminals
SOCKET A TERMINAL
NAME
SOCKET B TERMINAL
NAME
I/O
DESCRIPTION
NUMBER
NUMBER
A_CCLK
B08
B_CCLK
H17
O
CardBus clock. CCLK provides synchronous timing for all transactions on
the CardBus interface. All signals except CRST, CCLKRUN, CINT,
CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are sampled on the
rising edge of CCLK, and all timing parameters are defined with the rising
edge of this signal. CCLK operates at the PCI bus clock frequency, but it can
be stopped in the low state or slowed down for power savings.
A_CCLKRUN
C02
B_CCLKRUN
B17
I/O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an
increase in the CCLK frequency, and by the PCI6x20 device to indicate that
the CCLK frequency is going to be decreased.
A_CRST
C06
B_CRST
E19
O
CardBus reset. CRST brings CardBus PC Card-specific registers,
sequencers, and signals to a known state. When CRST is asserted, all
CardBus PC Card signals are placed in a high-impedance state, and the
PCI6x20 device drives these signals to a valid logic level. Assertion can be
asynchronous to CCLK, but deassertion must be synchronous to CCLK.