參數(shù)資料
型號(hào)： PCT789T-A
英文描述： PCI HSP56 World MicroModem/PCT303DW/PCT1789W
中文描述： 世界MicroModem/PCT303DW/PCT1789W的PCI HSP56
文件頁(yè)數(shù)： 10/70頁(yè)
文件大?。?/td> 872K
代理商： PCT789T-A
PC-TEL, Inc.
10
1789W0DOCDAT06A-0299
PCT1789W DATA SHEET
PCT789T-A P
IN
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
PCT789T-A P
IN
D
ESCRIPTION
Table 3 PCT789T-A Pin Description
Name
Numbers
I/O
Typ
e
Description
System Bus Interface Signals
AD[31:16]
90-94,
96-98,
1-8
22-25,
26-28,
30-37,
40
99,10,
20,29
t/s
PCI
Dual-purpose pins. Address/data bus bits [31:16]. Address and data are
multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases.
Address/data bus bits [15:0]. Address and data are multiplexed on the
same PCI pins. A bus transaction consists of an address phase fol-
lowed by one or more data phases.
AD[15:0]
t/s
PCI
C/BE[3:0]*
t/s
PCI
Bus command/byte enables pins. During the address phase of a trans-
action, C/BE[3:0]* define the bus command. During the data phase C/
BE[3:0]* are used as byte enables.
Clock. This is a input clock signal which provides timing for all transac-
tions on PCI.
PCI Device select. When actively driven, indicates the driving device has
decoded its address as the target of the current access. As an input,
DEVDEL* indicates whether any device on the bus has been selected.
PCI
Frame. This signal is driven by the current master to indicate the begin-
ning and duration of an access. While FRAME* is asserted, data trans-
fer continues. When FRAME* is deasserted, the transaction is in the
final data phase.
PCI
Grant. This signal indicates that PCT789T-A access request to the PCI
bus has been granted.
NOTE: The PCI master mode is not supported in this version, but the pin
is reserved for future expansion.
PCI
Initialization device select. This signal is active when the host wants to
do configuration read and write transactions.
PCI
Interrupt A. This is a level sensitive output which is used to request an
interrupt by PCT789T-A.
PCI
Initiator ready. This signal indicates the initiating agent’s ability to com-
plete the current data phase of the transaction.
PCI
Parity. This signal should be even parity across AD[31:00] and C/
BE[3:0]*. PAR is stable and valid one clock after the address phase.
PCI
Parity error. This signal is driven active when a data parity error is
detected.
PCI
Request. This signal is driven when the PCT789T-A desires use of the
PCI bus.
NOTE: The PCI master mode is not supported in this version, but the pin
is reserved for future expansion.
ST
Reset. This signal brings PCI-specific registers, sequencers, and sig-
nals to a consistent state. When active, the chip is returned to its initial
state with all the internal registers set at their default value.
PCI
Stop. This signal indicates the current target is requesting the master to
stop the current transaction.
CLK
86
I
PCI
DEVSEL*
14
s/t/s
FRAME*
11
s/t/s
GNT*
87
t/s
IDSEL
100
t/s
INTA*
83
OD
IRDY*
12
s/t/s
PAR
19
t/s
PERR*
17
s/t/s
REQ*
88
t/s
RST*
84
I
STOP*
15
s/t/s
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