參數資料
型號： PCT789T-A
英文描述： PCI HSP56 World MicroModem/PCT303DW/PCT1789W
中文描述： 世界MicroModem/PCT303DW/PCT1789W的PCI HSP56
文件頁數： 20/70頁
文件大小： 872K
代理商： PCT789T-A
PC-TEL, Inc.
20
1789W0DOCDAT06A-0299
PCT1789W DATA SHEET
PCT303DW F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
The digital interface consists of a single, synchronous
serial link which communicates both telephony and
control data.
In Serial mode 0 or 1, the PCT303D operates as a
master, where the master clock (MCLK) is an input, the
serial data clock (SCLK) is an output, and the frame
sync signal (FSYNC) is an output. The MCLK frequency
and the value of the sample rate control registers 7, 8, 9
and 10 determine the sample rate (Fs). The serial port
clock, SCLK, runs at 256 bits per frame, where the frame
rate is equivalent to the sample rate. Refer to “Clock
Generation Subsystem” on page 23 for more details on
programming sample rates.
The PCT303DW transfers 16-bit or 15-bit telephony
data in the primary timeslot and 16-bit control data in the
secondary timeslot. Figure 11 and Figure 12 show the
relative timing of the serial frames. Primary frames occur
at the frame rate and are always present. To minimize
overhead in the external DSP, secondary frames are
present only when requested.
Two methods exist for transferring control information in
the secondary frame. The default power-up mode uses
the LSB of the 16-bit transmit (TX) data word as a flag to
request a secondary transfer. In this mode, only 15-bit
TX data is transferred, resulting in a loss of SNR but
allowing software control of the secondary frames. As
an alternative method, the FC pin can serve as a
hardware flag for requesting a secondary frame. The
external DSP can turn on the 16-bit TX mode by setting
the SB bit of register 1. In the 16-bit TX mode, the
hardware FC pin must be used to request secondary
transfers.
Figure 13 and Figure 14 illustrate the secondary frame
read cycle and write cycle, respectively. During a read
cycle, the R/W bit is high and the 5-bit address field
contains the address of the register to be read. The
contents of the 8-bit control register are placed on the
SDO signal. During a write cycle, the R/W bit is low and
the 5-bit address field contains the address of the
register to be written. The 8-bit data to be written
immediately follows the address on SDI. Only one
register can be read or written during each secondary
frame. See “PCT303DW Control Registers” on page 41
for the register addresses and functions.
In serial mode 2, the PCT303D operates as a slave
device, where the MCLK is an input, the SCLK is a no
connect, and the FSYNC is an input. In addition, the
RGDT/FSD pin operates as a delayed frame sync (FSD)
and the FC/RGDT pin operates as ring detect (RGDT).
Note that in this mode, FC operation is not supported.
XMT Data
Secondary
Update
FSYNC
Primary
Secondary
Primary
Communications Frame 1 (CF1)
(CF2)
FC
0
Secondary
Update
XMT Data
RCV Data
D15-D1 D0=1 (Software FC Bit)
128 SCLKs
256 SCLKs
16 SCLKS
SDI
SDO
RCV Data
Figure 11 Software FC/RGDT Secondary Request
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