參數(shù)資料
型號(hào): PCT789T-A
英文描述: PCI HSP56 World MicroModem/PCT303DW/PCT1789W
中文描述: 世界MicroModem/PCT303DW/PCT1789W的PCI HSP56
文件頁(yè)數(shù): 30/70頁(yè)
文件大小: 872K
代理商: PCT789T-A
PC-TEL, Inc.
30
1789W0DOCDAT06A-0299
PCT1789W DATA SHEET
PCT789T-A PCI C
ONFIGURATION
R
EGISTERS
!
PRELIMINARY
PRELIMINARY
PCI Configuration Register Detailed Description
Configuration ID
(00h, R)
Bit Definitions:
Command and Status Configuration
(04h, R/W)
Bit Definitions:
DID[15:0]
24
31
30
29
28
27
26
25
23
22
21
20
19
18
17
16
VID[15:0]
8
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
Bits
Name
DID[15:0]
Description
Device ID (R: default 789xh). Unique PCT789T-A ID number. The last three bits
of the ID are loaded into this register through three strapped input pins, IDID[2:0],
during the power-on reset period.
Vendor ID (R: default 134Dh). Specifies the manufacturer of the PCT789T-A:
PC-TEL Inc.
31:16
15:0
VID[15:0]
PERR SSERR
31
0
0
0
27
DEVSEL[1:0]
26
0
24
0
23
0
0
CAP
20
0
0
0
17
0
16
30
29
28
25
22
21
19
18
0
0
0
0
0
11
0
10
0
9
SERREN
8
1
7
RSPPE
6
0
5
0
4
0
3
0
2
0
1
IOACS
0
15
14
13
12
Bits
Name
PERR
Description
Detected parity error (R/W: default 0b). Set when the PCT789T-A detects a par-
ity error.
Signaled system error (R/W: default 0b). Set when the PCT789T-A asserts
SERR#.
Reserved. Read returns zero.
DEVSEL timing (R: default 01b). Indicates the timing of the assertion of the
DEVSEL* pin. The PCT789T-A is set for median speed PCI device.
Reserved. Read returns zero.
Capabilities (R: default 1b). When set, indicates that the PCT789T-A is capable
of handling PCI power management.
Reserved. Read returns zero.
System error enable (R/W: default 0b). When set, enables the SERR# driver on
the PCT789T-A to report a system error.
Reserved. Read returns one.
Parity error response (R/W: default 0b). When set, signals the PCT789T-A to
assert PERR* after a parity error detection. Otherwise, any parity error detection
is ignored. Parity checking is disabled after reset.
Reserved. Read returns zero.
I/O space access (W). Set to allow the PCT789T-A to respond to I/O space
accesses.
31
30
SSERR
29:27
26:25
Reserved
DEVSEL[1:0]
24:21
20
Reserved
CAP
19:9
8
Reserved
SERREN
7
6
Reserved
RSPPE
5:1
0
Reserved
IOACS
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