參數(shù)資料
型號： PCT789T-A
英文描述： PCI HSP56 World MicroModem/PCT303DW/PCT1789W
中文描述： 世界MicroModem/PCT303DW/PCT1789W的PCI HSP56
文件頁數(shù)： 23/70頁
文件大?。?/td> 872K
代理商： PCT789T-A
PC-TEL, Inc.
23
1789W0DOCDAT06A-0299
PCT1789W DATA SHEET
PCT303DW F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
After the first PLL has been setup, the second PLL can
be programmed easily. The values for N2 and M2
(register 9) are shown in Table 10. N2 and M2 are 4-bit
unsigned values.
When programming the registers of the clock generator,
the order of register writes is important. For PLL1
updates, N1 (register 7) must always be written first,
immediately followed by a write to M1 (register 8). For
PLL2, the CGM bit must set as desired prior to writing
N2/M2 (register 9). Changes to CGM only take effect
when N2/M2 are written.
NOTE: The values shown in Table 10 and Table 11
satisfy
the
equations
programming the registers for N1, M1, N2, and M2, the
value placed in these registers must be one less than
the value calculated from the equations. For example,
for CGM = 0 with a MCLK of 48.0 MHz, the values
placed in the N1 and M1 registers would be 7Ch and
5Fh, respectively. If CGM = 1, a non-zero value must be
programmed to register 9 in order for the 16/25 ratio to
take effect.
above.
However,
when
PLL Lock Times
The PCT303DW changes sample rates very quickly.
However, lock time varies based on the programming of
the clock generator. The major factor contributing to PLL
lock time is the CGM bit. When the CGM bit is used (set
to one), PLL2 locks slower than when CGM is zero. The
following relationships describe the boundaries on PLL
locking time:
PLL1 lock time < 1 ms (CGM = 0,1)
PLL2 lock time <100 us (CGM = 0)
PLL2 lock time <1 ms (CGM = 1)
For modem designs, it is recommended that PLL1 be
programmed
during
initialization.
programming of PLL1 is necessary. The CGM bit and
PLL2 can be programmed for the desired initial sample
rate, typically 7200 Hz. All further sample rate changes
are made by simply writing to register 9 to update PLL2.
No
further
The final design consideration for the clock generator is
the update rate of PLL1. The following criteria must be
satisfied in order for the PLLs to remain stable:
Where F
UP1
is shown in Figure 15.
Setting Generic Sample Rates
The above clock generation description focuses on the
common modem sample rates. An application may
require a sample rate not listed in Table 10, such as the
common audio rate of 11.025 kHz. The restrictions and
equations above still apply; however, a more generic
relationship between MCLK and Fs (the desired sample
rate) is needed. The following equation describes this
relationship:
÷
M1
VCO1
P
D
÷
25
÷
N2
P
D
0
1
0
1
÷
16
MCLK
8 bits
8 bits
F
UP1
F
PLL1
F
PLL2
4 bits
1024Fs
PLL1
F
UP2
CGM
CGM
÷
N1
÷
5
÷
M2
4 bits
PLL2
VCO2
Figure 15 Clock Generation Subsystem
FUP1
FMCLK
N1
(
)
=
144
kHz
≥
N1 N2
M1 M2
ratio
Fs
MCLK
5 1024
=
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