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PEB 20321
PEF 20321
Local Bus Interface (LBI)
Data Sheet
163
2001-02-14
6.3
LBI Data Mode State Machine (DMSM)
The Data Mode State Machine (DMSM) in the Local Bus Interface will service the FIFOs
in specific devices such as the Siemens ESCC2 (SAB 82532), FALC54 (PEB 2254) or
HSCX (SAB 82525, SAB 82526). The state machine has user-programmable registers
to correctly handshake with the peripheral to transfer data. The DMSM registers are
directly accessible from the PCI host side.
In the slave EBC mode, the Mailbox registers are accessible from the local bus side to
facilitate communication between the PCI host system and the Local Bus host μC.
The MUNICH32X provides 4 DMA controllers to service two full duplex serial channels
on the LBI (e.g., to connect an ESCC2).
The Tx DMACs deliver DWORDs from the memory to the LBI TFIFO, and the Rx DMACs
transfer the DWORDs from LBI RFIFO to the host memory. The EBC is responsible for
‘
funneling
’
the DWORDs to the 8 or 16-bit local bus.
6.3.1
The Data Mode State Machine (DMSM) services packet data from peripheral FIFOs and
transfers them to the host memory via the DMACs.
The DMSM assists in transferring data from peripheral devices based on the Siemens
HDLC controller family (HSCX, ESCC2, FALC54).
The procedure makes it easy for the software to transmit packets queued in the shared
memory. Similarly, received packets are stored conveniently in the shared memory.
The data transfers via the LBI interface are processed in two different modes:
Interrupt mode and
DMA assisted mode.
The two modes can be selected for channel A/B by programming the bit fields
LCONF.MDA/MDB of LBI Configuration register. Note that devices such as the ESCC2
and HSCX support both modes, whereas the FALC54 supports only the interrupt mode.
The choice of a particular method will be application dependent.
DMSM Function
6.3.2
In the interrupt mode of data transfer, the DMSM interrogates certain pre-defined
interrupt status registers of the LBI peripherals (addressed by DMSM/LBI Indirect
External Configuration registers LREG0
…
LREG5), and takes action based on the
status of certain data FIFO related status bits. Note that all other status bits are ignored
by the DMSM but passed on to the host via the interrupt queue.
When an interrupt from a LBI peripheral is detected and not masked, the LBI Pass
Trough Interrupt Vector is generated and written to the address specified in Peripheral
Interrupt Queue Base Address (PIQBA) register.
Data Transfer in Interrupt Mode