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PEB 20321
PEF 20321
Reset and Initialization
Data Sheet
204
2001-02-14
Software Reset
For the subfunctions, the states described in
Table 17
can also be reached by
programming bits (19:17) in PCIRES register (refer to
Chapter 5.1.2
); i.e., setting those
bits to
‘
1
’
has the same effect for the subfunction as an external RST = low. Resetting
the bits to
‘
0
’
corresponds to deasserting RST for that function.
SSC
bit CONF.SSC must be set to
‘
1
’
GPDIR and GPDATA register values must be programmed to the
desired I/O function (refer to SSC section)
bit CONF.IOM must be set to
‘
1
’
IOM
-2
IOM
-2 operated with double data rate:
special settings of registers MODE1 and MODE2 are necessary:
bit fields MODE1.PCM(3:0) must be programmed to 8
H
bit fields MODE1.TTS(2:0) must be programmed to 0
H
bit fields MODE1.RTS(2:0) must be programmed to 0
H
bit fields MODE1.TBS(2:0) must be programmed to 3
H
bit fields MODE1.RBS(2:0) must be programmed to 5
H
bit MODE2.RXF must be programmed to
‘
0
’
bit MODE2.TXR must be programmed to
‘
0
’
bit MODE2.RSF must be programmed to
‘
0
’
bit MODE2.TSR must be set to
‘
1
’
bit IOMCON1.CLR must be set to
‘
1
’
bit IOMCON1.ENIH must be set to
‘
1
’
IOM
-2 operated with single data rate:
special settings of registers MODE1 and MODE2 are necessary:
bit fields MODE1.PCM(3:0) must be programmed to 8
H
bit fields MODE1.TTS(2:0) must be programmed to 0
H
bit fields MODE1.RTS(2:0) must be programmed to 0
H
bit fields MODE1.TBS(2:0) must be programmed to 4
H
bit fields MODE1.RBS(2:0) must be programmed to 2
H
bit MODE2.RXF must be programmed to
‘
0
’
bit MODE2.TXR must be programmed to
‘
1
’
bit MODE2.RSF must be programmed to
‘
0
’
bit MODE2.TSR must be set to
‘
1
’
bit IOMCON1.CLR must be set to
‘
0
’
bit IOMCON1.ENIH must be set to
‘
1
’
Table 22
Subfunction
Programming after Hardware Reset
Required Register Programming