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| 型號： | pentium II |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II processor With On-die Cache Mobile Module Connector 1 (MMC-1)(帶緩存和連接器1的奔II處理器) |
| 中文描述： | 奔騰II處理器芯片上緩存手機(jī)模塊連接器1（MMC管理- 1）（帶緩存和連接器1的奔二處理器） |
| 文件頁數(shù)： | 12/34頁 |
| 文件大小： | 582K |
| 代理商： | PENTIUM II |
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12
Intel
a
Pentium
a
II Processor With On-die Cache Mobile Module MMC-1
3.1.5
Power Management (8 Signals)
Table 5 lists the power management interface signals. The
SM_CLK and SM_DATA signals refer to the two-wire serial
SMBus interface. Although this interface is currently used
solely for the digital thermal sensor, the SMBus contains
reserved serial addresses for future use. See section 4.9 for
more details.
Table 5. Power Management Signal Descriptions
Voltage
Name
Type
Description
OEM_PU
I
CMOS
N/C
CMOS
I
CMOS
I
V_3
OEM Pullup:
This pullup resistor is not required on the module.
L2_ZZ
V_CPUIO
Low-Power Mode For Cache SRAM:
This signal is not used on the module.
SUS_STAT#
V_3ALWAYS
1
Suspend Status:
This signal connects to the SUS_STAT1# outputs of PIIX4E/M. It
provides information on host clock status and is asserted during all suspend states.
VR_ON
V_3
VR_ON:
Voltage regulator ON.
This 3.3-V (5.0-V tolerant) signal controls the
operation of the voltage regulator.
VR_ON should be generated as a function of the
PIIX4E/M SUSB# signal, which is used for controlling the “Suspend State B” voltage
planes. This signal should be driven by a digital signal with a rise/fall time of less
than or equal to 1 us. (VIL(max)=0.4V, VIH(min)=3.0V.) See Figure 5, “Power-on
Sequence Timing” for proper sequencing of VR_ON.
VR_PWRGD
O
V_3
VR_PWRGD:
This signal is driven high to indicate that the voltage regulator is
stable and is pulled low using a 100K resistor when inactive.
It can be used in some
combination to generate the system PWRGOOD signal.
SM_CLK
I/O D
CMOS
V_3
Serial Clock:
This clock signal is used on the SMBus interface to the digital thermal
sensor. Ensure proper termination based upon the
System Management Bus
Specification, Revision 1.0
.
SM_DATA
I/O D
CMOS
V_3
Serial Data:
An open-drain data signal on the SMBus interface to the digital thermal
sensor. Ensure proper termination based upon the
System Management Bus
Specification, Revision 1.0
.
ATF_INT#
O D
CMOS
V_3
ATF Interrupt:
This signal is an open-drain output signal of the digital thermal
sensor.
NOTE:
V_3ALWAYS: 3.3V supply. It is generated whenever V_DC is available and supplied to PIIX4E/M resume well.
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