參數(shù)資料
型號(hào): pentium II
廠商: Intel Corp.
英文描述: pentium II processor With On-die Cache Mobile Module Connector 1 (MMC-1)(帶緩存和連接器1的奔II處理器)
中文描述: 奔騰II處理器芯片上緩存手機(jī)模塊連接器1(MMC管理- 1)(帶緩存和連接器1的奔二處理器)
文件頁數(shù): 26/34頁
文件大?。?/td> 582K
代理商: PENTIUM II
26
Intel
a
Pentium
a
II Processor With On-die Cache Mobile Module MMC-1
4.6.2.1
BCLK Signal Quality Specifications and
Measurement Guidelines
Table 17 describes the signal quality specifications at the
processor core for the BCLK signal. Figure 4 describes the
signal quality waveform for the BCLK at the processor core
pins.
Table 17. BCLK Signal Quality Specifications at the Processor Core
Parameter
Min
Max
Unit
BCLK V
IL
2
0.7
V
V2:
1.8
V
V
IN
Absolute Voltage Range
3
-0.8
3.5
V
V4:
1.8
V
Falling Edge Ringback
4
0.7
V
T#
V1:
BCLK V
IH
2
V3:
Rising Edge Ringback
4
V5:
BCLK rising/falling slew-rate
0.8
4
V/ns
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
2.
BCLK must rise and fall monotonically between VIL,BCLK and VIH, BCLK.
The mobile Pentium II processor with on-die cache PSB clock overshoot and undershoot specification for 66-
MHz operation.
3.
4.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
For proper signal termination, refer to the Clocking Guidelines in the
Mobile Pentium
a
II Processor / 440BX
PCIset Advanced Platform Recommend Design and Debug Practices.
5.
V2
V1
V3
V3
T3
V5
V4
T6
T4
T5
000806
Figure 4. BCLK, TCK, and PICCLK Generic Clock Waveform at the Processor Core Pin
4.7
The Voltage Regulator
The DC voltage regulator (DC/DC converter) provides the
appropriate core voltage, the I/O ring voltage, and the
sideband signal pullup voltage for the Pentium II processor
with on-die cache mobile module. The voltage range is 5
volts to 21 volts.
4.7.1
Voltage Regulator Efficiency
Table 18 lists the voltage regulator efficiencies.
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