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參數(shù)資料
| 型號： | pentium II |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II processor With On-die Cache Mobile Module Connector 1 (MMC-1)(帶緩存和連接器1的奔II處理器) |
| 中文描述： | 奔騰II處理器芯片上緩存手機(jī)模塊連接器1（MMC管理- 1）（帶緩存和連接器1的奔二處理器） |
| 文件頁數(shù)： | 30/34頁 |
| 文件大小： | 582K |
| 代理商： | PENTIUM II |
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30
Intel
a
Pentium
a
II Processor With On-die Cache Mobile Module MMC-1
Table 21. Capacitance Requirements per Power Plane
Capacitance Requirements
Power Plane
ESR
Ripple Current
Rating
V_DC
100 uf, 0.1 uf, 0.01 uf
1
20 m
1-3.5A
3
20% tolerance at 35V
V_5
100 uf, 0.1 uf, 0.01 uf
1
100 m
1A
20% tolerance at 10V
V_3
470 uf, 0.1 uf, 0.01 uf
1
100 m
1A
20% tolerance at 6V
V_3S
100 uf, 0.1 uf, 0.01 uf
1
100 m
N/A
20% tolerance at 6V
V_CPUIO
2
2.2 uf, 8200 pf
1
N/A
N/A
20% tolerance at 6V
NOTES:
1.
Placement of above capacitance requirements should be located near the connector.
2.
V_CPUIO filtering should be located next to the system clock synthesizer.
3.
Ripple current specification depends on V_DC input. For 5.0-V V_DC, a 3.5-A device is required.
4.
For V_DC at 18V or higher, 1A is sufficient.
4.7.4
Surge Current Guidelines
This section provides the results of a worst case, surge
current analysis. The analysis determines the maximum
amount of surge current that the Pentium II processor with
on-die cache mobile module MMC-1 can manage.
In the analysis, the module has two 4.7 microfarads with an
ESR of 0.15 ohms total. The MMC-1 connector is
approximately 30 milliohms of series resistance, for a total
series resistance of .18 ohms. If the user powers the system
with the A/C adapter (18 volts), the amount of surge current
on the module would be approximately 100 amperes. This
information is also used to develop I/O bulk capacitance
requirements. See Table 20 for more information.
Note
: Depending on the system electronics design, different
impedances may yield different result. A thorough analysis
should be performed to understand the implications of surge
current on their system.
Figure 6 shows an electrical model used when analyzing
instantaneous power-on conditions, and Figure7 illustrates
the results with a SPICE simulation.
Figure 6. Instantaneous In-rush Current Model
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