![](http://datasheet.mmic.net.cn/330000/PM7366_datasheet_16444405/PM7366_156.png)
RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
143
Register 0x29C : RMAC Packet Descriptor Reference Large Buffer Free Queue Write
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
R/W
RPDRLFQW[15]
0
Bit 14
R/W
RPDRLFQW[14]
0
Bit 13
R/W
RPDRLFQW[13]
0
Bit 12
R/W
RPDRLFQW[12]
0
Bit 11
R/W
RPDRLFQW[11]
0
Bit 10
R/W
RPDRLFQW[10]
0
Bit 9
R/W
RPDRLFQW[9]
0
Bit 8
R/W
RPDRLFQW[8]
0
Bit 7
R/W
RPDRLFQW[7]
0
Bit 6
R/W
RPDRLFQW[6]
0
Bit 5
R/W
RPDRLFQW[5]
0
Bit 4
R/W
RPDRLFQW[4]
0
Bit 3
R/W
RPDRLFQW[3]
0
Bit 2
R/W
RPDRLFQW[2]
0
Bit 1
R/W
RPDRLFQW[1]
0
Bit 0
R/W
RPDRLFQW[0]
0
This register provides the Packet Descriptor Reference Large Buffer Free Queue write address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
RPDRLFQW[15:0]:
The receive packet descriptor reference (RPDR) large buffer free queue write bits
(RPDRLFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large
Buffer Free Queue write pointer. This register is initialised by the host. The physical write
address in the RPDRLF queue is the sum of RPDRLFQW[15:0] left shifted by 2 bits with the
RQB[31:0] bits in the RMAC Receive Queue Base register.