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| 型號(hào)： | PM7366 |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER |
| 中文描述： | 8 CHANNEL(S), 52M bps, SERIAL COMM CONTROLLER, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁(yè)數(shù)： | 65/286頁(yè) |
| 文件大?。?/td> | 2243K |
| 代理商： | PM7366 |
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RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
52
performed according to the “byte address invariance” rule, i.e. the only change to the data is the
mirror-imaging of byte lanes.
The interface for the RMAC provides for byte addressability of write transactions whereas the
interface for the TMAC provides for byte addressability of read transactions. Other transactions
must be dword aligned. For byte-addressable transactions, the data transferred between the local
device and the GPIC need not be dword aligned with the data as it is presented on the PCI bus.
The GPIC will perform any byte-realignment required. In order to complete a transfer involving
byte re-alignment, the GPIC may need to add an extra burst cycle to the PCI transaction.
9.5.3
Target Machine
The GPIC target machine performs all the required functions of a stand alone PCI target device.
The target block performs three main functions. The first is the target state machine which
controls the protocol of PCI target accesses to the GPIC. The second function is to provide all
PCI Configuration registers. Last, the target block provides a Target Interface to the CBI registers
in the other FREEDM-8 blocks.
The GPIC tracks the PCI bus and decodes all addresses and commands placed on the bus to
determine whether to respond to the access. The GPIC responds to the following types of PCI
bus commands only: Configuration read and write, memory read and write, memory-read-multiple
and memory-read-line which are aliased to memory read and memory-write-and-invalidate which
is aliased to memory write. The GPIC will ignore any access that falls within the address range
but has any other command type.
After accepting a target access as a medium speed device, the FREEDM inserts one wait state
for a configuration read/write and five wait states for other command types before completing the
transaction by asserting TRDYB.
Burst accesses to the GPIC are accepted provided they are of linear type. If a master makes a
memory access to the GPIC with the lower two address bits set to any value but "00" (linear burst
type) the GPIC ignores the cycle. Burst accesses of any length are accepted, but the FREEDM
will disconnect if the master inserts any wait states during the transaction. The FREEDM will also
disconnect on every read and write access to configuration space after transferring one Dword of
data.
Figure 9 illustrates the GPIC address space.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM7366-BI | TVS BI-DIR 30V 1500W DO-201 |
| PM7366-PI | FRAME ENGINE AND DATA LINK MANAGER |
| PM7367-PI | DIODE 1N4002 RECTIFYING |
| PM7367 | 32 link, 32 Channel Data Link Manager with PCI Interface |
| PM7375 | ATM SAR and PHY Processor for PCI Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7366-BI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER |
| PM7366-PI | 制造商:PMC-Sierra 功能描述: |
| PM7367 | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER |
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