![](http://datasheet.mmic.net.cn/330000/PM7367-PI_datasheet_16444408/PM7367-PI_306.png)
DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
292
The PCI Bus Request Cycle Diagram (Figure 32) illustrates the case when the
initiator is requesting the bus from the bus arbiter.
When the FREEDM-32P32 is the initiator, it requests the PCI bus by asserting its
REQB output to the central arbiter. The arbiter grants the bus to the FREEDM-
32P32 by asserting the GNTB line. The FREEDM-32P32 will wait till both the
FRAMEB and IRDYB lines are idle before starting its access on the PCI bus.
The arbiter can remove the GNTB signal at any time, but the FREEDM-32P32
will complete the current transfer before relinquishing the bus.
Figure 32 – PCI Bus Request Cycle
PCICLK
REQB
1
2
3
4
5
6
T
GNTB
FRAMEB
The PCI Initiator Abort Termination Diagram (Figure 33) illustrates the case when
the initiator aborts a transaction on the PCI bus.
An initiator may terminate a cycle if no target claims it within five clock cycles. A
target may not have responded because it was incapable of dealing with the
request or a bad address was generated by the initiator. IRDYB must be valid
one clock after FRAMEB is deasserted as in a normal cycle. When the
FREEDM-32P32 is the initiator and aborts the transaction, it reports the error
condition to the PCI Host.