
DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
68
block. Writing new provisioning data to a channel resets the channel's entire
state vector.
8.7.2 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 8 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO Figure 15 shows an example of three blocks (blocks 1, 3, and 200)
linked together to form a 48 byte channel FIFO. The three pointer values would
be written sequentially using indirect block write accesses. When a channel is
provisioned with this FIFO, the state machine can be initialised to point to any
one of the three blocks.
The partial packet buffer processor is divided into three sections: reader, writer
and roamer. The roamer is a time-sliced state machine which tracks each
channel's FIFO buffer free space and signals the writer to service a particular
channel. The writer requests data from the TMAC block and transfers packet
data from the TMAC to the associated channel FIFO. The reader is a time-sliced
state machine, which transfers the HDLC information from a channel FIFO to the
HDLC processor when the HDLC processor requests it. If a buffer under-run
occurs for a channel, the reader informs the HDLC processor and purges the
rest of the packet.