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參數(shù)資料
| 型號(hào)： | PM7367 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | 32 link, 32 Channel Data Link Manager with PCI Interface |
| 中文描述： | 32連接，32通道數(shù)據(jù)鏈路管理器與PCI接口 |
| 文件頁(yè)數(shù)： | 85/323頁(yè) |
| 文件大?。?/td> | 2429K |
| 代理商： | PM7367 |
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DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
71
and time-slot identity, the TCAS performs a table look-up to identify the channel
from which a data byte is to be sourced.
Links may also be unchannelised. Then, all data bytes on that link belong to one
channel. The TCAS performs a table look-up to identify the channel to which a
data byte belongs using only the outgoing link identity, as no time-slots are
associated with unchannelised links. Link clocks are no longer limited to T1 or
E1 rates and may range up to 52 MHz for TCLK[2:0]. For TCLK[31:3] the
maximum clock rate is 10 MHz. The link clock is only active during bit times
containing data to be transmitted and inactive during bits that are to be ignored
by the downstream devices, such as framing and overhead bits. For the case of
two unchannelised links, the maximum link rate is 45 MHz for SYSCLK at
25 MHz and 52 MHz for SYSCLK at 33 MHz. For the case of more numerous
unchannelised links or a mixture of channelised and unchannelised links, the
total instantaneous link rate over all the links is limited to 64 MHz.
8.8.1 Line Interface
There are two types of line interfaces in the TCAS; high-speed and low-speed
interfaces. Three identical high-speed interfaces are attached to the first three
links, while 29 identical low-speed interfaces are attached to the remaining links.
Each line interface contains a bit counter, an 8-bit shift register and a byte FIFO,
that, together, perform parallel to serial conversion. For the high-speed
interfaces the FIFO is six bytes deep. For the low-speed interfaces, the FIFO is
a single byte holding register. Whenever the shift register is updated, a request
for service is sent to the priority encoder block. The request will eventually be
serviced by the THDL block and the data is written into the FIFO.
To support channelised links, each line interface block contains a time-slot
counter and a clock activity monitor. The time-slot counter is incremented each
time the shift register is updated. The clock activity monitor is a counter that
increments at the system clock (SYSCLK) rate and is cleared by a rising edge of
the transmit clock (TCLK[n]). A framing bit (T1) or framing byte (E1) is detected
when the counter reaches a programmable threshold. At which point, the bit and
time-slot counters are initialised to indicate the next bit sampled is the most
significant bit of the first time-slot. For unchannelised links, the time-slot counter
and the clock activity monitor are held reset.
8.8.2 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from line interface TD[0] to
line interface TD[31]. Thus, simultaneous requests from line interface TD[m] will
be serviced ahead of line interface TD[n], if m < n. The priority encoder selects
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