
DATA SHEET
PM7367 FREEDM-32P32
ISSUE 2
PMC-1991499
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
42
Figure 6 – RPDRF and RPDRR Queues
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
Status + RPDR
Status + RPDR
Status + RPDR
Status + RPDR
Status + RPDR
Status + RPDR
RQB[31:2] = Rx Queue Base register
RPDRRQS[15:0]
RPDRRQW[15:0] = RPDR Ready Queue Write register
RPDRRQR[15:0]
= RPDR Ready Queue Read register
RPDRRQE[15:0]
= RPDR Ready Queue End register
= RPDR Ready Queue Start register
Receive Packet Descriptor (RPD) Reference Queues
Base Address:
Index Registers:
Ready Queue:
RPDRSFQS[15:0] = RPDR Small Free Queue Start register
RPDRSFQW[15:0] = RPDR Small Free Queue Write register
RPDRSFQR[15:0] = RPDR Small Free Queue Read register
RPDRSFQE[15:0] = RPDR Small Free Queue End register
Large Buffer Free Queue:
RPDRLFQS[15:0] = RPDR Large Free Queue Start register
RPDRLFQW[15:0] = RPDR Large Free Queue Write register
RPDRLFQR[15:0] = RPDR Large Free Queue Read register
RPDRLFQE[15:0] = RPDR Large Free Queue End register
Small Buffer Free Queue:
Base Address
+ Index Register
-------------------------
Host Address
00
RQB[31:2]
Index[15:0]
+
AD[31:0]
Rx Packet Descriptor Reference Queue Memory
M
Bit 31
RPDRRQS
RQB
Bit 0
Valid RPDR
256KB
RPD Reference Queues
Host Memory
RPDRRQW
RPDRRQR
RPDRRQE
RPDRLFQS
RPDRLFQW
RPDRLFQR
RPDRLFQE
RPDRSFQS
RPDRSFQR
RPDRSFQW
RPDRSFQE
00