參數(shù)資料
型號(hào): PSD713S5
英文描述: Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述: 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能(可編程邏輯,4K的位的SRAM,27余個(gè)可編程輸入/輸出,通用PLD的有66個(gè)輸入)
文件頁數(shù): 16/104頁
文件大?。?/td> 515K
代理商: PSD713S5
PSD7XX Family
13-16
Each of the three PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Decode PLD
The Decode PLD (DPLD), shown in Figure 4, is used to select the internal PSD7XX
functions: EPROM blocks, SRAM, Registers (CSIOP) and the Port A Peripheral Mode.
All the select signals are active high and have one product term, except ES7 which has two.
The CSIOP is the select line for the PSD7XX internal registers that occupies 256 bytes
of memory space. A second level decoder selects a register based on the address
inputs A[7-0].
Each EPROM block has its own chip select. The chip select of the eighth EPROM
block has two product terms, ES7A and ES7B. This allows the eighth block to reside
in two memory spaces, where ES7B can typically select reset vectors or configuration
bytes that are stored in the MCU address space.
PSEL 0 & 1 are used as inputs to Port A to control the port’s Peripheral I/O mode
operation. Usually PSEL 0&1 are defined in term of the MCU address inputs. This mode is
explained in the I/O Port section.
PLDs
(cont.)
Input Source
Input Name
Number of Bits
MCU Address Bus
A[15:0]
*
16
I/O Ports
Port A, B, C
PA[7:0], PB[7:0],
PC[7:0]
24
Page Register
PGR[3:0]
4
Control Signal
CNTL1 (Read)
1
Supervisory Function
GRESET or ERESET
1
Supervisory Function
WDOG_ON
1
Table 8. DPLD Inputs
*
NOTE:
The address inputs are A[19:4] in 80C51XA mode. A[3:0] are assigned to Port A.
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