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| 型號： | PSD713S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入） |
| 文件頁數(shù)： | 64/104頁 |
| 文件大小： | 515K |
| 代理商： | PSD713S5 |
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PSD7XX Family
13-64
Power
Management
Unit
(cont.)
Other Power Saving Options
The PSD7XX offers other reduced power saving options that are independent of the
Power Down or Sleep Mode. Except for the SRAM Standby and CSI input features, they are
enabled by setting bits in the PMMR 0 register.
J
CMiser Bit
The CMiser bit resides in PMMR0. This bit controls the AC power consumption and
access time of the EPROM and SRAM. When in 8 bit data bus mode and CMiser is set,
the PSD7XX will consume the lowest level of AC power. However, the access time will
be slower (see CMiser adder in timing parameters). When CMiser bit is off, the AC
power is higher and the PSD7XX will return to standard access time.
J
SRAM Standby Mode
The SRAM has a Vstby pin (PC2) that can be connected to a battery. When V
CC
becomes lower than Vstby then the PSD7XX will automatically connect the Vstby as
a power source to the SRAM. The SRAM Standby Current (Istby) is typically 0.5μA.
SRAM data retention voltage is 2V minimum.
J
The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input . When low, the signal
selects and enables the internal EPROM and SRAM for read or write operations.
A high on the CSI pin will disable the EPROM and SRAM and reduce the PSD power
consumption. However, the PLD remains operational when CSI is high.
J
Input Clock
The PSD7XX provides the option to turn off the CLKIN and the Supervisory Clock
input to the PLD to save AC power consumption. The CLKIN is an input to the PLD
AND array and the Output Micro
Cells. During power down or if any of the CLKIN
input is not being used as part of the PLD logic equation, the clock should be disabled
to save AC power.
The CLKIN will be disconnected from the PLD AND array or the Micro
Cells by
setting bit 4 or 5 to “1” in the PMMR0.
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