參數(shù)資料
型號： PSD713S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入）
文件頁數(shù)： 68/104頁
文件大?。?/td> 515K
代理商： PSD713S5
PSD7XX Family
13-68
Reset Generation
The PSD7XX can generate output reset signals that go out to the external peripherals and
the microcontroller. Three sources are capable of issuing reset:
J
Power-On reset; voltage comparator with programmable internal or external trip point.
J
Push button or system reset input from the RST pin.
J
WatchDog Timer timeout output when enabled
The microcontroller can read the PSD7XX Status Register to determine the source of the
reset. The internal global reset (GRESET) can be brought out to pins on Port C as an
active low or high output. The width of the extended reset output (ERESET) pulse is user
configurable and is controlled by the Programmable Pulse Generator. Either GRESET or
ERESET (active high) can be declared as an internal node in PSDabel and participate in
the logic equation definition.
Push Button Reset Input
The PSD7XX has a dedicated active-low reset input pin that can be connected to a
system reset or a push button reset. The system reset is a direct input to the reset
generator, while the Push Button input is routed through a selectable debouncer filter that
filters out transitions shorter than three clock cycles. The clock source of this debouncer is
either a 125Hz internal oscillator or CLKIN/128K.
Figure 46 shows the reset pin input timing requirement. The active low range has a
minimum tNLNH duration. After the rising edge of reset, the PSD7XX remains in the reset
state during tOPR range. Table 37 shows the I/O pin status of the PSD7XX during the reset
and power down mode.
Supervisory
Function
(cont.)
Port Configuration
Reset
Power Down Mode
MCU I/O
Input
Unchanged
PLD Output
Active
Depends on inputs to
the PLD
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Table 37. Status During Reset and Power Down Mode
Register
Reset
Power Down Mode
PMMR0 & 1
Cleared (power up reset)
Unchanged
Unchanged (warm reset)
Micro
Cell Flip-Flop
Unchanged
*
Unchanged
*
All other registers
Cleared to “0”
Unchanged
*
The Micro
Cell flip-flop can be cleared or set by the reset input or the PDN (Power Down) signal, depending on
the .re and .pr equations that are defined in the PSDabel file.
相關(guān)PDF資料
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PSD813F Flash In-System-Programmable Microcontroller Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
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