參數(shù)資料
型號(hào)： PSD713S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入）
文件頁(yè)數(shù)： 26/104頁(yè)
文件大小： 515K
代理商： PSD713S5
PSD7XX Family
13-26
PLDs
(cont.)
Peripheral PLD
The Peripheral PLD (PPLD), shown in Figure 10, controls the operation of the WatchDog
Timer of the Supervisory Function. The input to the PPLD consists of the same 66 signals
that are shared with the GPLD (refer to Table 7). The PPLD provides two active high
outputs, each consists of one product term:
J
WDOG_EN
The WatchDog Timer can be enabled either by the trailing edge of the reset generated
by the Supervisory Function, or by an active high WDOG_EN pulse. The WDOG_EN
product term can be defined to become active when the microcontroller writes to a
certain address. The WDOG_EN signal can be activated only after the external reset
(ERESET) expires.
J
WDOG_CLR
This is an active high pulse that re-loads the counter in the WatchDog Timer and
prevents the WatchDog from generating a timeout. The WDOG_CLR product term can
be defined to become active when the microcontroller writes to a specific address.
GRESET or ERESET
PLD INPUT BUS
WDOG–EN
WDOG–ON
SUPERV–CLK
SUPERVISORY
FUNCTION
WATCHDOG
TIMER
WDOG–CLR
Figure 10. PPLD Logic Array
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