參數(shù)資料
型號(hào)： PSD713S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入）
文件頁數(shù)： 63/104頁
文件大?。?/td> 515K
代理商： PSD713S5
PSD7XX Family
13-63
Bit 0
0 = ALE power down polarity low
1 = ALE power down polarity high
0 = Automatic Power Down (APD) is disabled
1 = Automatic Power Down (APD) is enabled
0 = EPROM/SRAM CMiser is off
1 = EPROM/SRAM CMiser is on
0 = CLKIN input to the PLD AND array is connected
Every CLKIN change will power up the PLD when Turbo bit is off
1 = CLKIN input to PLD AND array is disconnected
0 = CLKIN input to the PLD Micro
Cells is connected
1 = CLKIN input to the PLD Micro
Cells is disconnected
0 = Supervisory Clock input to the GPLD is connected
1 = Supervisory Clock input to the GPLD is disconnected
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
Superv
clk
PLD
Mcell clk
PLD
Array clk
*
CMiser
APD
Enable
ALE PD
Polarity
1 = off
1 = off
1 = off
1 = on
1 = on
1 = high
Table 33. Power Management Mode Registers (PMMR0, PMMR1)**
PMMR0
*
*
Bits 3 and 7 are not used, and should set to 0.
**
Both the PMMR0 and PMMR1 register bits are clear to zero following power up.
Subsequent reset pulses will not clear the registers.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
Sleep
Mode
Enable
1 = on
APD
Clk
Source
1= CLKIN
PMMR1
Bit 0
0 = Supervisory Clock serves as APD clock
1 = CLKIN serves as the APD clock
0 = Sleep Mode is Disabled
1 = Sleep Mode is Enabled
Bit 1
*
Unused bits should be set to 0.
APD
ALE
Enable Bit
PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
Table 34. APD Counter Operation
Power
Management
Unit
(cont.)
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