參數(shù)資料
型號： PSD713S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入）
文件頁數(shù)： 79/104頁
文件大?。?/td> 515K
代理商： PSD713S5
PSD7XX Family
13-79
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
V
IH
V
IL
V
IH1
V
IH2
V
IL1
V
HYS
Supply Voltage
All Speeds
4.5
5
5.5
V
High Level Input Voltage
4.5 V < V
CC
< 5.5 V
4.5 V < V
CC
< 5.5 V
(Note 1)
2
V
CC
+.5
0.8
V
Low Level Input Voltage
–0.5
V
Reset High Level Input Voltage
.8 V
CC
V
CC
+.5
V
CC
+.5
.2 V
CC
–.1
V
V
TP
Pin
Reset Low Level Input Voltage
V
(Note 1)
–.5
V
Reset Pin Hysteresis
0.3
V
5% V
CC
= 5V, V
tp
(2:0) = 0
10% V
CC
= 5V, V
tp
(2:0) = 6
V
tp
(2:0) = 7, No Power On
Reset
4.47
4.61
4.75
V
V
TP
Power Supply Trip Point
4.08
4.29
4.50
V
0
V
V
ETP
External Trip Point (PC6)
1.23
1.29
1.35
V
V
OL
Output Low Voltage
I
OL
= 20 μA, V
CC
= 4.5 V
0.01
0.1
V
I
OL
= 8 mA, V
CC
= 4.5 V
I
OH
= –20 μA, V
CC
= 4.5 V
0.15
0.45
V
V
OH
Output High Voltage
Except VSTBYON, CEOUT
4.4
4.49
V
I
OH
= –2 mA, V
CC
= 4.5 V
I
OH1
= 1 μA
2.4
3.9
V
V
OH1
V
SBY
I
SBY
I
IDLE
V
DF
Output High Voltage VSTBYON, CEOUT
V
SBY
–0.5
V
CC
1
SRAM Standby Voltage
2.0
V
SRAM Standby Current
V
CC
= 0 V
V
CC
> V
SBY
Only on V
STBY
0.5
μA
Idle Current (V
STBY
Pin)
SRAM Data Retention Voltage
–0.1
0.1
μA
2
V
I
SB
Standby Supply
Current
Power Down Mode
CSI >V
CC
–.3 V (Note 2)
CSI >V
CC
–.3 V (Note 3)
V
SS
< V
IN
> V
CC
.45 < V
IN
> V
CC
50
100
μA
Sleep Mode
25
50
μA
I
LI
I
LO
Input Leakage Current
–1
±.1
1
μA
Output Leakage Current
–10
±5
10
μA
PLD Only
f = 0 MHz
400
700
μA/PT
CMiser = ON
and Not Selected
0
0
mA
CMiser = ON and EPROM
Selected (x8 Data Bus)
EPROM Adder
10
15
mA
I
CC
(DC)
(Note 4)
Operating
Supply Current
CMiser = ON and EPROM
Selected (x16 Data Bus)
15
20
mA
CMiser = OFF
15
20
mA
SRAM Not Selected
0
0
mA
CMiser = ON, SRAM
Selected (x8 Data Bus)
SRAM Adder
25
40
mA
CMiser = ON, SRAM
Selected (x16 Data Bus)
30
45
mA
I
CC
(AC)
PLD
2
3
mA/MHz
EPROM or SRAM
2
mA/MHz
DC Characteristics
(5 V ± 10% Versions)
NOTES:
1.
Reset input has hysteresis. V
IL1
is valid at or below .2V
CC
–.1. V
IH1
is valid at or above .8V
CC
.
CSI deselected or internal PD is active.
Sleep mode bit is set and internal PD is active.
I
OUT
= 0 mA.
2.
3.
4.
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