參數(shù)資料
型號(hào)： PSD813FN
英文描述： Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
中文描述： 場(chǎng)可編程微控制器外圍設(shè)備（帶閃存的現(xiàn)場(chǎng)可編程微控制器）
文件頁(yè)數(shù)： 19/83頁(yè)
文件大?。?/td> 369K
代理商： PSD813FN
Prelimnary
PSD813FN/FH
19
Loading and Reading the Micro
Cells
The GPLD Micro
Cells occupy a memory location in the MCU address space as defined
by the CSIOP (refer to the I/O section). The Flip-Flops in each of the 12 Micro
Cells can
be loaded from the data bus by a microcontroller write bus cycle to the Micro
Cell
(see I/O Port section for Micro
Cell Addresses). A “1” in the data bit that associates with
the Micro
Cell will load a “1” to the Flip-Flop, a “0” in the data bit will load a “0” to the
Flip-Flop. The loading bus cycle takes priority over other Flip-Flop inputs that include the
Preset, Clear and clock. See Table 11 for the data bits that are connected to the
Micro
Cells. The ability to load the flip-flops and read them back is useful in such
applications as loadable counters, shift registers, mailboxes or handshaking protocols.
PLDs
(cont.)
LD
1
1
0
Dn
1
0
X
Clk
X
X
In
X
X
PR
X
X
CLR
X
X
Q
1
0
Normal Flip-Flop Function
Table 11. Micro
Cell Flip-Flop Loading
NOTE:
LD is “1” when the MCU writes to the Micro
Cell address
The Output Enable
The Micro
Cell can be connected to a PSD813FN/FH I/O pin as PLD output. The output
enable of each of the Port pin output driver is controlled by a single product term (.oe) from
the AND array ORed with the Direction Register output. Upon power up, if no output enable
(.oe) equation is defined and the pin is declared as a PLD output in PSDsoft, the pin is
enabled.
If the Micro
Cell output is declared as internal node and not as Port pin output in the
PSDabel file, then the Port pin can be used for other I/O functions (such as MCU I/O mode).
The internal node feedback can be routed as an input to the AND array.
Input Micro
Cell
The Input Micro
Cell as shown in Figure 6 is used to latch, register or pass incoming
Port signals prior to driving them onto the PLD Input bus. The outputs of these Micro
Cells
can also be read by the microcontroller through the internal Data Bus. The GPLD has 23
Input Micro
Cells, one for each pin of Ports A, B and C (except PC2). The Input
Micro
Cells are individually configurable.
The enable/clock for the latch and flip-flop is driven by a multiplexor whose inputs are a
product term from the GPLD AND array and the MCU address strobe (ALE). Each
product term output is used to latch/clock four Input Micro
Cells. Port inputs [3:0] can be
controlled by one product term and [7:4] can be controlled by another one.
The Input Micro
Cell configurations are specified by equations written in PSDabel.
Outputs of the Micro
Cells can be read by the microcontroller via the “Input Micro
Cell”
buffer. See the I/O Port section on how to read the Micro
Cells.
Input Micro
Cells can use the ALE to latch the higher address bits (A31 – A16). The
latched addresses are routed to the PLD as inputs.
The Input Micro-Cell is particularly useful in handshaking communication applications where
two processors wish to pass data between each other through a commonly accessible
storage. Figure 7 shows a typical configuration where the Master MCU writes to the Port A
Data Out Register that is read by the Slave MCU via the activation of the “Slave-Read”
output enable product term. The Slave MCU can write to Port A Input Micro
Cells by
activating the “Slave- Wr” product term. The Master MCU can then read the Input
Micro
Cells. The “Slave-Read” and “Slave-Wr” signals are product terms that are derived
from the Slave MCU inputs of RD, WR, and Slave_CS.
相關(guān)PDF資料
PDF描述
PSD813FH Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
PSD82 Three Phase Rectifier Bridges
PSD834F2V Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲(chǔ)器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.)
PSD834F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
PSD835G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲(chǔ)器可編程外設(shè))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD833F2-90M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD833F2-90MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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