參數(shù)資料
型號： PSD813FN
英文描述： Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器)
中文描述： 場可編程微控制器外圍設備（帶閃存的現(xiàn)場可編程微控制器）
文件頁數(shù)： 35/83頁
文件大?。?/td> 369K
代理商： PSD813FN
Prelimnary
PSD813FN/FH
35
I/OPorts
(cont.)
Port Data Registers
(cont.)
Register I/OAddress Ofset
The base address of the Registers is defined in the CSIOP equation that occupies
256 bytes of address space and is defined by the user in PSDsoft. The lower address byte
A[7:0], or address offset, selects the register. Table 22 shows the address offset for all
MCUs except those Motorola microcontrollers with a 16-bit data bus.
For example, when the CSIOP is defined to occupy the address range of 1000h to 10FFh in
PSDabel, the address of the Port A Control Register is then 1002h.
Register Name
Port A
Port B
Port C
Port D
Data In
Control
Data Out
Direction
Drive
Input Micro
Cell
Enable Out
Output Micro
Cell
00
02
04
06
08
0A
0C
20
01
03
05
07
09
0B
0D
20
10
11
12
14
16
18
1A
21
13
15
17
Table 22. I/ORegister Address Ofset (relative to CSIOP)
Microcontroller
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8-Bit
Multiplexed Bus
(PSD813FH)
8-Bit
Non-Multiplexed Bus
(PSD813FN)
Address (3:0)
Address (7:4)
Address (3:0)
Address (7:4)
N/A
N/A
Address (3:0)
Address (7:4)
Table 23. I/OPort Latched Address Output Assignments
Port A and B – Functionality and Structure
Port A and B have similar functionality and structure as shown in Figure 14. The two ports
can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
GPLD Output – Micro
Cells McellAB[7:4] can be connected to Port A PA[7:4}
or Port B PB[7:4].
J
ECSPLD Output – External chip select output can be connected to either Port A
PA[3:0] or Port PB[3:0].
J
Latched Address output – Provide latched address output per Table 23.
J
Address In – Additional high address inputs using the Input Micro
Cells.
J
Open Drain/Slew Rate – pins PA[3:0] and PB[3:0] can be configured to Open Drain Mode
pins PA[7:4] and PB[7:4] can be configured to fast slew rate
J
Data Port – Port A to D[7:0} for 8 bit non-multiplexed bus
J
Peripheral Mode – Port A only
N/A = Not Applicable.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813FN-15J 制造商:WSI 功能描述:
PSD833F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD833F2-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD833F2-90M 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD833F2-90MI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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