參數(shù)資料
型號: PSD813FN
英文描述: Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器)
中文描述: 場可編程微控制器外圍設(shè)備(帶閃存的現(xiàn)場可編程微控制器)
文件頁數(shù): 48/83頁
文件大?。?/td> 369K
代理商: PSD813FN
PSD813FN/FH
Prelimnary
48
Bit 0
0 = ALE power down polarity low
1 = ALE power down polarity high
0 = Automatic Power Down (APD) is disabled
1 = Automatic Power Down (APD) is enabled
0 = EPROM/SRAM CMiser is off
1 = EPROM/SRAM CMiser is on
0 = CLKIN input to the PLD AND array is connected
1 = CLKIN input to PLD AND array is disconnected
0 = CLKIN input to the PLD Micro
Cells is connected
1 = CLKIN input to PLD Micro
Cells is disconnected
Bit 1
Bit 2
Bit 4
Bit 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
PLD
Mcell clk
PLD
Array clk
*
CMiser
APD
Enable
ALE PD
Polarity
1 = off
1 = off
1 = on
1 = on
1 = high
Table 28. Power Management Mode Registers (PMMR0, PMMR1)**
PMMR0
*
*
Bits 3, 6 and 7 are not used, and should set to 0.
**
Both the PMMR0 and PMMR1 register bits are clear to zero following power up.
Subsequent reset pulses will not clear the registers.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
Sleep
Mode
Enable
1 = on
*
PMMR1
Bit 1
0 = Sleep Mode is Disabled
1 = Sleep Mode is Enabled
*
Unused bits should be set to 0.
APD
ALE
Enable Bit
PD Polarity
ALE Level
APDCounter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
Table 29. APDCounter Operation
Power
Management
Unit
(cont.)
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相關(guān)代理商/技術(shù)參數(shù)
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PSD813FN-15J 制造商:WSI 功能描述:
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PSD833F2-90MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100