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參數(shù)資料
| 型號： | PSD813FN |
| 英文描述： | Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 78/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FN |
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PSD813FN/FH
Prelimnary
78
Instructions and Commands
The Command Interface (C.I.) latches commands written to the memory. Instructions are
made up from one or more commands to perform Reset, Read Electronic Signature, Sector
Erase, Bulk Erase, Program, Sector Erase Suspend and Erase Resume. Commands are
made of address and data sequences. Addresses are latched on the falling edge of WRF or
CSF and data is latched on the rising of WRF or CSF. The instructions require from 1 to 6
cycles, the first or first three of which are always write operations used to initiate the
command. They are followed by either further write cycles to confirm the first command or
execute the command immediately. Command sequencing must be followed exactly. Any
invalid combination of commands will reset the device to Read Array. The increased
number of cycles has been chosen to assure maximum data security. Commands are initial-
ized by two preceding coded cycles which unlock the Command Interface. In addition, for
Erase, command confirmation is again preceded by the two coded cycles.
P/E.C. status is indicated during command execution by Data Polling on D7, detection of
Toggle on D6, or Error on D5 and Erase Timer D3 bits. Any read attempt during Program
or Erase command execution will automatically output those four bits. The P/E.C.
automatically sets bits D3, D5, D6 and D7. Other bits (D0, D1, D2 and D4) are reserved for
future use and should be masked.
J
Data Polling Bit DQ7
When Programming operations are in progress, this bit outputs the complement of the
bit being programmed on D7. During Erase operation, it outputs a ‘0’. After completion
of the operation, D7 will output the bit last programmed or a ‘1’ after erasing. Data
Polling is valid only effective during P/E.C. operation, that is after the fourth WRF pulse
for programming or after the sixth WRF pulse for Erase. It must be performed at the
address being programmed or at an address within the sector being erased. If the byte
to be programmed belongs to a protected sector the command is ignored. If all the
sectors selected for erasure are protected, D7 will set to ‘0’ for about 100 μs, and then
return to previous addressed memory data. See Figure 2 for the Data Polling flowchart.
Appendix A –
Flash Memory
(cont.)
A18
1
1
1
1
0
0
0
0
TOP
ADDRESS
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
BOTTOM
ADDRESS
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
A17
1
1
0
0
1
1
0
0
A16
1
0
1
0
1
0
1
0
64K Bytes Sector
64K Bytes Sector
64K Bytes Sector
–
–
–
64K Bytes Sector
64K Bytes Sector
Figure 1. Memory Map and Sector Address Table
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相關(guān)代理商/技術(shù)參數(shù) |
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| PSD813FN-15J | 制造商:WSI 功能描述: |
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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