參數(shù)資料
型號(hào)： PSD834F2V
英文描述： Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲(chǔ)器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.)
中文描述： 閃光私營(yíng)部門(mén)，3.3V電源，為8位微控制器2兆256千位雙閃存和64千位的SRAM（200萬(wàn)位256K位雙路閃速存儲(chǔ)器和64K的位靜態(tài)內(nèi)存，閃速私營(yíng)部門(mén)，3.3V的電源，用于8位微控制器。）
文件頁(yè)數(shù)： 23/89頁(yè)
文件大?。?/td> 522K
代理商： PSD834F2V
23/89
PSD834F2V
Reset Flash.
The Reset Flash instruction con-
sists of one Write cycle (see Table 7). It can also
be optionally preceded by the standard two write
decoding cycles (writing AAh to 555h and 55h to
AAAh). It must be executed after:
– Reading theFlash Protection Statusor FlashID
– An Error condition has occurred (and the device
has set the Error Flag (DQ5) bit to 1) during a
Flash memory Program or Erase cycle.
The Reset Flash instructionputs theFlash memo-
ry back into normal Read mode. If an Error condi-
tion has occurred (and the device has set the Error
Flag (DQ5) bit to 1) the Flash memory is put back
into normal Read mode within 25
μ
s of the Reset
Flash instruction having been issued. The Reset
Flash instruction is ignored when it is issued dur-
ing a Program or Bulk Erase cycle of the Flash
memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the
Flash memory to the normal Read mode within
25
μ
s.
Reset (RESET) Signal.
A pulse on Reset (RE-
SET) aborts any cycle that is in progress, and re-
sets the Flash memory to the Read mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25
μ
s to return to
the Read mode. It is recommended that the Reset
(RESET) pulse (except for Power On Reset, as
described onpage 60) beat least 25
μ
s sothat the
Flash memory is always ready for the MCU to
fetch the bootstrap instructions after the Reset cy-
cle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (VSTBY, PC2). If you have an
external battery connected to the PSD, the con-
tents of the SRAM are retained in the event of a
power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn fromthe external bat-
tery. Battery-on Indicator (VBATON, PC4) is High
with thesupply voltage falls below the battery volt-
age and the battery on Voltage Stand-by(VSTBY,
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Configu-
ration.
Sector Select and SRAM Select
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDabel. The following rules apply to the
equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must notbe larg-
er than the physical sector size.
2. Any primary Flash memory sector must not be
mapped in the same memory space as another
Flash memory sector.
3. A secondary Flash memory sector must not be
mapped in the same memory space as another
secondary Flash memory sector.
4. SRAM, I/O, and Peripheral I/O spaces must not
overlap.
5. A secondary Flash memory sector may overlap
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
Example.
FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 isvalid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of theprimary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also note that an equation that de-
fined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
相關(guān)PDF資料
PDF描述
PSD834F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速I(mǎi)SP外圍)
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PSD835G2 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA Tabless package; Similar to IRHMJ57160 with optional Total Dose Rating of 1000kRads
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD834F2V-15J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-15M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-20JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-20MI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD835G2-70U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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