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參數(shù)資料
| 型號： | PSD834F2V |
| 英文描述： | Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.) |
| 中文描述： | 閃光私營部門，3.3V電源，為8位微控制器2兆256千位雙閃存和64千位的SRAM（200萬位256K位雙路閃速存儲器和64K的位靜態(tài)內(nèi)存，閃速私營部門，3.3V的電源，用于8位微控制器。） |
| 文件頁數(shù)： | 55/89頁 |
| 文件大小： | 522K |
| 代理商： | PSD834F2V |
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PSD834F2V
POWER MANAGEMENT
All PSD devices offer configurable power saving
options. These options maybe used individually or
in combinations, as follows:
I
All memory blocks in a PSD (primary and
secondary Flash memory, and SRAM) are built
with power management technology.In addition
to using special silicon design methodology,
power management technology puts the
memories into standby mode when address/
data inputs are not changing (zero DC current).
As soon as a transition occurs on an input, the
affected memory “wakes up”, changes and
latches its outputs, then goes back to standby.
The designer does not have to do anything
special toachieve memory standby mode when
no inputs are changing—it happens
automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as de-
scribed in the sections on the Power Manage-
ment Mode Registers (PMMR).
I
As with the Power Management mode, the
Automatic Power Down (APD) block allows the
PSD to reduce to stand-by current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs. This feature is available
on all the devices of the PSD family. The APD
Unit is described in more detail in the sections
entitled “AutomaticPower-down(APD) Unit and
Power-down Mode”, on page 56.
Built inlogic monitorsthe Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain time period (MCU is asleep), the APD Unit
initiates Power-down mode (ifenabled). Once in
Power-down mode,all address/data signals are
blocked from reaching PSD memory and PLDs,
and the memories are deselected internally.
This allows the memory and PLDs to remain in
standby mode even if the address/data signals
are changing state externally (noise, other de-
vices on the MCU bus, etc.). Keep in mind that
any unblocked PLD input signals that are
changing states keeps the PLD out of Stand-by
mode, but not the memories.
I
PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in standby mode even if inputs are changing.
This feature does notblock any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit. There is a slight penalty
in memory access time when PSD Chip Select
Input (CSI, PD2) makes its initial transition from
deselected to selected.
I
The PMMRs can be written by the MCU at run-
time to manage power. All PSD supports
“blocking bits” in these registers that are set to
block designated signals from reaching both
PLDs. Current consumption of the PLDs is
directly related to the composite frequency of
the changes on their inputs (see Figure 32).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations.
PSD devices have a Turbo bit in PMMR0. This
bit can beset to turn theTurbo mode off(the de-
fault is with Turbo modeturned on). While Turbo
mode is off, the PLDs can achieve standby cur-
rent when no PLD inputs are changing (zero DC
current). Even when inputs do change, signifi-
cant power can be saved at lower frequencies
(AC current), compared to when Turbomode is
on. When the Turbo mode is on, there is a sig-
nificant DC current component and theAC com-
ponent is higher.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD834F2V-15J | 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2V-15M | 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2V-20JI | 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2V-20MI | 功能描述:SPLD - 簡單可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD835G2-70U | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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