參數(shù)資料
型號: Q67120-C1056SAB-C501G-1EP
英文描述: IC-8-BIT CPU
中文描述: 集成電路8位CPU
文件頁數(shù): 103/121頁
文件大?。?/td> 1000K
代理商: Q67120-C1056SAB-C501G-1EP
Device Specifications
C501
Semiconductor Group
10-6
AC Characteristics for C501-L / C501-1R / C501-1E
(cont’d)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
12 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 12 MHz
min.
6
t
CLCL
– 100
6
t
CLCL
– 100
t
CLCL
– 53
min.
max.
max.
RD pulse width
t
RLRH
t
WLWH
t
LLAX2
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
WHLH
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
400
ns
WR pulse width
400
ns
Address hold after ALE
30
5
t
CLCL
– 165
2
t
CLCL
– 70
8
t
CLCL
– 150
9
t
CLCL
– 165
3
t
CLCL
+ 50
t
CLCL
+ 40
ns
RD to valid data in
252
ns
Data hold after RD
0
0
ns
Data float after RD
97
ns
ALE to valid data in
517
ns
Address to valid data in
585
3
t
CLCL
– 50
4
t
CLCL
– 130
t
CLCL
– 40
t
CLCL
– 50
7
t
CLCL
– 150
t
CLCL
– 50
ns
ALE to WR or RD
200
300
ns
Address valid to WR or RD
203
ns
WR or RD high to ALE high
43
123
ns
Data valid to WR transition
33
ns
Data setup before WR
433
ns
Data hold after WR
33
ns
Address float after RD
0
0
ns
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 12 MHz
min.
max.
Oscillator period
t
CLCL
t
CHCX
t
CLCX
t
CLCH
t
CHCL
83.3
285.7
t
CLCL
t
CLCX
t
CLCL
t
CHCX
20
ns
High time
20
ns
Low time
20
ns
Rise time
ns
Fall time
20
ns
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